Patents by Inventor Jong-Ru Guo
Jong-Ru Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230369289Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Jong-Ru Guo, Zhen Zhou, Jason Mix, Chia-Pin Chiu, Zuoguo Wu
-
Patent number: 11599497Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: GrantFiled: August 31, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
-
Patent number: 11450613Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.Type: GrantFiled: March 23, 2018Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Mayue Xie, Jong-Ru Guo, Zhiguo Qian, Zuoguo Wu
-
Publication number: 20220206064Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.Type: ApplicationFiled: December 24, 2020Publication date: June 30, 2022Inventors: Zhen ZHOU, Renzhi LIU, Jong-Ru GUO, Kenneth P. FOUST, Jason A. MIX, Kai XIAO, Zuoguo WU, Daqiao DU
-
Publication number: 20210399764Abstract: An apparatus comprises a crosstalk cancelation circuit comprising a plurality of taps to output signals based on a signal transmitted via a first data line; and a summation circuit to combine a signal received by a second data line with the signals output by the plurality of taps to reduce near-end crosstalk present in the signal received by the second data line.Type: ApplicationFiled: September 1, 2021Publication date: December 23, 2021Applicant: Intel CorporationInventors: Jingbo Li, Beom-Taek Lee, Jong-Ru Guo, Yunhui Chu, Chunfei Ye, Kai Xiao
-
Publication number: 20210311120Abstract: An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Jong-Ru Guo, Jingbo Li, Xiaoning Ye, Zuoguo Wu, Howard L. Heck
-
Patent number: 11116072Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.Type: GrantFiled: November 17, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Jun Liao, Zhen Zhou, James A. McCall, Jong-Ru Guo, Xiang Li, Yunhui Chu, Zuoguo Wu
-
Patent number: 10965047Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: GrantFiled: June 4, 2019Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
-
Patent number: 10908206Abstract: Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.Type: GrantFiled: May 17, 2016Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Mayue Xie, Chengqing Hu, Jong-Ru Guo, Zuoguo Wu, Deepak Goyal
-
Publication number: 20200394151Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Applicant: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
-
Patent number: 10789201Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: GrantFiled: June 29, 2017Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
-
Patent number: 10729002Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.Type: GrantFiled: July 18, 2019Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Jun Liao, Xiang Li, Yunhui Chu, Jong-Ru Guo, James McCall
-
Publication number: 20190342990Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Jun Liao, Xiang Li, Yunhui Chu, Jong-Ru Guo, James McCall
-
Publication number: 20190293708Abstract: Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.Type: ApplicationFiled: May 17, 2016Publication date: September 26, 2019Applicant: Intel CorporationInventors: Mayue Xie, Chengqing Hu, Jong-Ru Guo, Zuoguo Wu, Deepak Goyal
-
Publication number: 20190295953Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Mayue XIE, Jong-Ru GUO, Zhiguo QIAN, Zuoguo WU
-
Publication number: 20190288421Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
-
Publication number: 20190045622Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.Type: ApplicationFiled: November 17, 2017Publication date: February 7, 2019Inventors: Jun LIAO, Zhen ZHOU, James A. McCALL, Jong-Ru GUO, Xiang LI, Yunhui CHU, Zuoguo WU
-
Publication number: 20180284185Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Mayue Xie, Zhiguo Qian, Jong-Ru Guo, Zhichao Zhang, Zuoguo Wu
-
Patent number: 10088518Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.Type: GrantFiled: March 30, 2017Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Mayue Xie, Zhiguo Qian, Jong-Ru Guo, Zhichao Zhang, Zuoguo Wu
-
Publication number: 20180253398Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: ApplicationFiled: June 29, 2017Publication date: September 6, 2018Inventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss