Patents by Inventor Jong-Ryul JUN

Jong-Ryul JUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083356
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 12, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum LIM, Jong-Ryul JUN, Eun-A KIM, Jong-Min LEE
  • Patent number: 10439048
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum Lim, Jong-Ryul Jun, Eun-A Kim, Jong-Min Lee
  • Publication number: 20180350957
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Application
    Filed: July 20, 2018
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum Lim, Jong-Ryul Jun, Eun-A Kim, Jong-Min Lee
  • Patent number: 10050129
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum Lim, Jong-Ryul Jun, Eun-A Kim, Jong-Min Lee
  • Publication number: 20170256628
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Application
    Filed: February 21, 2017
    Publication date: September 7, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum LIM, Jong-Ryul JUN, Eun-A KIM, Jong-Min LEE
  • Patent number: 9349724
    Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon-bae Kim, Yong-chul Oh, Kuk-han Yoon, Kyu-pil Lee, Jong-ryul Jun, Chang-hyun Cho, Gyo-young Jin
  • Patent number: 8860115
    Abstract: A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Ryul Jun
  • Publication number: 20130277724
    Abstract: A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 24, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-Ryul JUN