Patents by Inventor Jong-Ryun Choi
Jong-Ryun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139362Abstract: A sterilization apparatus includes a housing; a sterilization unit for irradiating, with sterilization light, at least one region to be sterilized; and a driving unit for moving the sterilization unit into and out of the housing via an opening of the housing and rotating the sterilization unit about a rotation axis.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Hyun Woo Choi, Sang Hyoung Lee, Jong Min Lee, Jong Woon Kim, Hae Ryun Lee, Man Young Chun, Hye Jin Park
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Patent number: 11381231Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.Type: GrantFiled: August 10, 2020Date of Patent: July 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwan Yeob Chae, Jong-Ryun Choi
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Patent number: 10977412Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.Type: GrantFiled: October 18, 2018Date of Patent: April 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan-Yeob Chae, Jong-Ryun Choi
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Publication number: 20200373919Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kwan Yeob CHAE, Jong-Ryun CHOI
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Patent number: 10840896Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.Type: GrantFiled: July 16, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwan Yeob Chae, Jong-Ryun Choi
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Patent number: 10756059Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.Type: GrantFiled: October 11, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwanyeob Chae, Sanghoon Joo, Jong-Ryun Choi, Jin-Ho Choi
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Patent number: 10572406Abstract: A memory controller for receiving a differential data strobe signal and an application processor having the memory controller are disclosed. The memory controller includes a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signal and output a first detection signal based on a level of each of the first and second strobe signals, a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal, and a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal using the first detection signal and the second detection signal.Type: GrantFiled: February 15, 2017Date of Patent: February 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hun Oh, Sang-hune Park, Jin-ho Choi, Jong-ryun Choi, Dae-ro Kim
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Publication number: 20190197214Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.Type: ApplicationFiled: October 18, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kwan-Yeob Chae, Jong-Ryun Choi
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Publication number: 20190199335Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.Type: ApplicationFiled: July 16, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kwan Yeob CHAE, Jong-Ryun CHOI
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Publication number: 20190043841Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.Type: ApplicationFiled: October 11, 2018Publication date: February 7, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: KWANYEOB CHAE, Sanghoon JOO, Jong-Ryun CHOI, Jin-Ho CHOI
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Patent number: 10115706Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.Type: GrantFiled: September 27, 2016Date of Patent: October 30, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwanyeob Chae, Sanghoon Joo, Jong-Ryun Choi, Jin-Ho Choi
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Patent number: 10073619Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.Type: GrantFiled: December 14, 2017Date of Patent: September 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
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Publication number: 20180165023Abstract: A memory controller for receiving a differential data strobe signal and an application processor having the memory controller are disclosed. The memory controller includes a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signal and output a first detection signal based on a level of each of the first and second strobe signals, a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal, and a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal using the first detection signal and the second detection signal.Type: ApplicationFiled: February 15, 2017Publication date: June 14, 2018Inventors: Ji-hun OH, Sang-hune PARK, Jin-ho CHOI, Jong-ryun CHOI, Dae-ro KIM
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Publication number: 20180107387Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Inventors: Kwanyeob Chae, Yoonjee NAM, Ji Hun OH, Shinyoung YI, Jong-Ryun CHOI
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Publication number: 20180018092Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.Type: ApplicationFiled: May 2, 2017Publication date: January 18, 2018Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
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Patent number: 9857973Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.Type: GrantFiled: May 2, 2017Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
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Patent number: 9859880Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.Type: GrantFiled: October 11, 2016Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan-Yeob Chae, Sang-Hoon Joo, Sang-Hune Park, Jong-Ryun Choi, Hoon-Koo Lee
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Publication number: 20170111033Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.Type: ApplicationFiled: October 11, 2016Publication date: April 20, 2017Inventors: KWAN-YEOB CHAE, SANG-HOON JOO, SANG-HUNE PARK, JONG-RYUN CHOI, HOON-KOO LEE
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Publication number: 20170098624Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.Type: ApplicationFiled: September 27, 2016Publication date: April 6, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwanyeob CHAE, Sanghoon JOO, Jong-Ryun CHOI, Jin-Ho CHOI
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Patent number: 8766691Abstract: A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.Type: GrantFiled: March 15, 2013Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Ryun Choi, Ji-Hun Oh, Choong-Bin Lim