Abstract: A system-on-a-chip sharing a graphics processing unit supporting multi-master is provided. A system on chip (SoC) comprises a plurality of central processing units (CPUs) for executing at least one operating system, a graphics processing unit (GPU) that is connected to each of the plurality of CPUs via a bus interface and communicates with each of the plurality of CPUs, and at least one state monitoring device that is selectively connected to at least one CPU among the plurality of CPUs and transmits execution state information of at least one operating system executed in the connected CPU to the GPU. The GPU is shared by at least one operating system and controls a sharing operation by the at least one operating system based on the execution state information of the at least one operating system.

Abstract: A system-on-a-chip sharing a graphics processing unit supporting multi-master is provided. A system on chip (SoC) comprises a plurality of central processing units (CPUs) for executing at least one operating system, a graphics processing unit (GPU) that is connected to each of the plurality of CPUs via a bus interface and communicates with each of the plurality of CPUs, and at least one state monitoring device that is selectively connected to at least one CPU among the plurality of CPUs and transmits execution state information of at least one operating system executed in the connected CPU to the GPU. The GPU is shared by at least one operating system and controls a sharing operation by the at least one operating system based on the execution state information of the at least one operating system.

Abstract: A system-on-a-chip sharing a graphics processing unit supporting multi-master is provided. A system on chip (SoC) comprises a plurality of central processing units (CPUs) for executing at least one operating system, a graphics processing unit (GPU) that is connected to each of the plurality of CPUs via a bus interface and communicates with each of the plurality of CPUs, and at least one state monitoring device that is selectively connected to at least one CPU among the plurality of CPUs and transmits execution state information of at least one operating system executed in the connected CPU to the GPU. The GPU is shared by at least one operating system and controls a sharing operation by the at least one operating system based on the execution state information of the at least one operating system.

Abstract: A static random access memory (SRAM) device is provided. A memory cell is supplied with a first driving voltage. A bit line pair is connected to the memory cell. A sense amplifier is connected to the bit line pair. The sense amplifier is supplied with a second driving voltage that is lower than the first driving voltage. A control logic selects a pre-charge voltage from the first and second driving voltages, pre-charges the bit line pair to the pre-charge voltage and adjusts the pre-charged voltage to a target voltage.

Abstract: A clock mesh circuit includes a first clock circuit, a second clock circuit, and a switch circuit. The first clock circuit includes a first clock mesh network, and is configured to transmit a received clock signal to a first load circuit. The second clock circuit includes a second clock mesh network separate from the first clock mesh network, and is configured to transmit the clock signal to a second load circuit. The switch circuit connects the first clock circuit to the second clock circuit. The switch circuit connects the first clock mesh network to the second clock mesh network. The clock mesh circuit is configured such that the clock signal is transmitted to the first and second load circuits when the switch circuit is turned-on, and the clock signal is transmitted to either the first load circuit or the second load circuit when the switch circuit is turned-off.

Abstract: A static random access memory (SRAM) device is provided. A memory cell is supplied with a first driving voltage. A bit line pair is connected to the memory cell. A sense amplifier is connected to the bit line pair. The sense amplifier is supplied with a second driving voltage that is lower than the first driving voltage. A control logic selects a pre-charge voltage from the first and second driving voltages, pre-charges the bit line pair to the pre-charge voltage and adjusts the pre-charged voltage to a target voltage.

Abstract: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A power source switching apparatus and method thereof are provided.

Abstract: A power source switching apparatus is provided. The example power source switching apparatus may include a voltage adjuster outputting a first power source voltage having a voltage level, corresponding to the output voltage of a battery, during an external power source mode where the battery is being charged, the first power source voltage based at least in part on the external power source and the output voltage of the battery, a controller outputting a first control signal and a second control signal, the first control signal enabled if the battery is operating in the external power source mode and the second control signal is enabled if the battery is not operating in the external power source mode, a first switch outputting the first power source voltage if the first control signal is enabled and a second switch outputting the output voltage of the battery if the second control signal is enabled.

Abstract: A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.

Abstract: A charging controller includes a control node having a control voltage generated thereon for controlling a first current to a charged device and a second current to a reference device. Feedback loops are formed with amplifiers and a pull-up current source and control transistors, or with amplifiers and transfer transistors, for maintaining the second current at a constant current level during a constant current mode and for maintaining a voltage of the charged device at a constant voltage level during a constant voltage mode. Use of a pull-down current source at the control node is avoided for preventing damage to the charged device.