Abstract: A method and device for decoding in a differential orthogonal space-time block coded system are disclosed. The disclosed method includes: (a) receiving signals from a transmitter during a particular time slot segment, where the signals are encoded by differential orthogonal space-time block coding; (b) transforming to reception signals for two sub-systems by using a sum operation and a difference operation of the signals received in step (a), where the transformed reception signals for the two sub-systems maintain an orthogonality of an orthogonal space-time block coded system; and (c) performing decoding using the reception signals for the two sub-systems transformed in step (b). The method provides the advantage of lowering the level of operational complexity for decoding in a communication system that employs differential orthogonal space-time block coding.

Abstract: A channel equalizer and a method of equalizing a channel.

Abstract: A memory address generator in a convolutional interleaver/deinterleaver for correcting errors occurred in a data transmission of communication systems.

Abstract: Disclosed is an apparatus and a method for generating decoding clock signals in response to a period of write and read clock signals for decoding transmission data, which is suppressed in a form of punctured code at a code rate. The apparatus according to the present invention comprises a) a clock generator receiving a control signal and a code rate from a transmission part, for rearranging a suppressed data; b) a controller receiving a write clock signal from an external circuit and a read clock signal from the clock generator, for controlling a period of a read clock signal wherein the period of the read clock signal is correspondent to the number of data stored in the memory; c) a decoding clock generator receiving a system clock signal from an external circuit and the control clock signal from the controller, for outputting a decoding clock signal.

Abstract: A method and apparatus for discriminating synchronous or asynchronous states of Viterbi decode data, by performing independent trace-back of the survival path of the received Viterbi decode data, including the steps of: tracing back independently reception data at respective initial states on the basis of trellis metrics from a different initial state value; and comparing a state value with other state values at every cycle, and determining that the data is in a synchronous state, if the state value is identical to the other state values at a cycle, or determining that the data is in an asynchronous state, if not.