Abstract: A timing controller to reduce a flicker in a display device is provided. The timing controller includes a line pattern detector and a frame pattern detector. The line pattern detector divides received data into a plurality of unit blocks and detects a line polarity of each of a plurality of horizontal lines included in each of the unit blocks. The frame pattern detector generates a polarity control signal to control a data inversion method based on a frame image pattern detected based on line polarities of the respective horizontal lines.

Abstract: In a method for digitally driving an AMOLED to display a plurality of different areas of the AMOLED including a first area displaying a first image and a second area displaying a second image, the method comprises: commencing display of at least one of a plurality of lines of the AMOLED to cause display of the first image beginning at a first area light emission start time of a sub-field period of the AMOLED frame period; and commencing display of at least one of a plurality of lines of the AMOLED to cause display of the second image beginning at a second area light emission start time of the sub-field period of the AMOLED frame period.

Abstract: In a timing controller and a liquid crystal display device having the same, the timing controller includes a line memory block receiving and storing pixel data received at a first data transfer frequency, and outputting the stored pixel data at a second data transfer frequency. A control unit, which is connected to an output terminal of the line memory block, transfers pixel data output from the line memory block to an external frame memory at the second data transfer frequency and outputting pixel data, which is transferred from the frame memory, after converting the pixel data to a predetermined data format.

Abstract: A method and circuit for controlling the brightness of a backlight in a display device. The circuit comprises a backlight brightness selecting block that measures the brightness of ambient light and selects brightness information of the backlight based on the measured brightness of the ambient light. An image processing block performs image processing on received image signal based on the measured brightness of the ambient light, and calculates an image processing gain of the received image signal based on the result of image processing and the received image signal. A backlight adjusting unit controls the brightness of the backlight based on the selected backlight brightness information and the image processing gain.

Abstract: Provided are frame interpolation apparatus and methods in which motion estimation is performed by separation into a static object and a moving object. The frame interpolation apparatus interpolates multiple frames including an nth frame and an (n?1)th frame located adjacent the nth frame in order to generate an interpolation frame. Some embodiments of the apparatus include a static object separation unit, a motion vector (MV) estimation unit, and an interpolation frame generation unit. The static object separation unit may compare a macroblock (MB) of the nth frame with an MB of the (n?1)th frame, which may correspond to the MB of the nth frame, in order to separate each MB of the nth frame into a static object and a moving object. The MV estimation unit may search in the (n?1)th frame for an MB that matches with each of MBs of the nth frame, which may be determined to be the moving object, to estimate an MV.

Abstract: A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

Abstract: A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

Abstract: A liquid crystal display includes a signal controller having a luminance controller receiving image data from an external graphic source and controlling the luminance of the image data such that the luminance at the gray expressed by a specific data value of the image data is established to be 80 cd/m2, and a gamma converter outputting image data each having a gamma characteristic adapted to a gamma 2.2 curve. The gamma converter output is determined without using a look up table based on at least one difference curve having a linear portion, a quartic portion, and a critical value where the liner portion and the quartic portion intersect. The liquid crystal display further includes a data driver receiving the image data for selecting and outputting gray voltages corresponding to the image data, and an inverter controlling a lamp to emit light with a luminance of 80 cd/m2 or more.

Abstract: A contrast control apparatus includes a memory for storing input image signals within one frame and an image reducing unit for selecting at least one image signal of the input image signals. An accumulation value calculating unit calculates accumulation values for predetermined sampling gray values with respect to the selected image signal. An image characteristic decision unit determines at least one characteristic of the selected image based on the accumulation values. A contrast control function calculating unit calculates a contrast control function based on the characteristic of the selected image. A contrast controller controls contrast of the image signals stored in the memory according to the contrast control function.

Abstract: A method of changing a pixel color includes determining whether a chrominance of a pixel is in a preference chrominance area, where the preference chrominance area is defined as a conic section in a two-dimensional chrominance plane and an eccentricity of the conic section is not greater than 1, and changing the chrominance of the pixel to a preference chrominance to generate a preference pixel when the chrominance of the pixel is in the to preference chrominance area. Therefore, the method may set a preference chrominance area in a simple manner, and hardware for setting the preference chrominance area may be easily implemented.

Abstract: A liquid crystal display module includes a liquid crystal display panel, a backlight assembly, a circuit board and a timing controller. The circuit board includes a first connector receiving a data signal and a second connector separated from the first connector and receiving a power supply voltage. The timing controller receives the power supply voltage from the second connector and the data signal from the first connector, and processes the data signal. The first connecter includes a first and a second integrated type connector, the second integrated type connector receiving image signals and control signals which controls operation of the liquid crystal display panel through the first integrated type connector from a user connecting part and providing image and control signals to the timing controller.

Abstract: An LCD for improving dynamic contrast by adjusting gamma voltages according to the brightness of an image is provided. The LCD includes: a liquid crystal display panel assembly having a plurality of pixels provided on crossing areas of a plurality of gate lines and a plurality of data lines; a gate driver applying voltage signals for sequentially scanning the gate lines; a source driver applying voltage signals for image display to the data lines; a timing controller providing image data and a control signal for the source driver, providing a gate line on/off control signal for the gate driver, and outputting digital gamma data to a digital/analogue (D/A) converter; and the D/A converter connected to the timing controller for converting the digital gamma data from the timing controller into analog signals to generate a plurality of gamma voltages and outputting the gamma voltages to the source driver.

Abstract: A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

Abstract: An LCD module includes a user connector part that receives power voltages, image signals and control signals from an external host system and outputs the power voltages, image and control signals through a first integrated type connector and an LCD module having a second integrated type connector connected with the first integrated type connector through an FPC. The LCD module receives power voltages and image and control signals through the second integrated type connector, provides image data signals and timing signals to data lines and provides scan signals to gate lines. Namely, the LCD can receive power voltage, the image signals and control signals through the integrated type connector instead of a plurality of connecting terminals, thereby providing an LCD having slim weight and compact size and reducing the size thereof.

Abstract: A variable-length decoder includes a bitstream interface unit and a decoding unit, The bitstream interface unit generates a decoding bitstream for a current decoding process based on an unused decoding bitstream and an input bitstream. The unused bitstream includes unused bits of a previous decoding bitstream. The decoding unit decodes the decoding bitstream to generate a plurality of symbols per clock cycle and provides a next unused bitstream for a next decoding process to the bitstream interface unit.

Abstract: A display driving apparatus and method adjusts output gray voltage levels applied to a display driving apparatus that converts input data into a corresponding output voltage and displays an image. The driving method includes generating a plurality of gray voltages N times more than the number of output gray voltages representing voltages between a maximum value and a minimum value of the output voltage required to represent the input data as the image; selecting a plurality of output gray voltages required to represent the image, from among the gray voltages N times more than the output gray levels, in response to a selection signal; and decoding the input data using the selected output gray voltages and generating the output voltage. The display driving apparatus and method reduce distortion of an output image without increasing the size of the entire circuit.

Abstract: A display driving circuit includes a first interface unit, a signal discriminating circuit, a signal distributing circuit, a driver logic circuit and a synchronization processing unit. The first interface unit receives a first signal through a first interface from a host. The signal discriminating circuit discriminates whether the first signal corresponds to a first video signal or a second video signal. The signal distributing circuit divides the first signal into the first and second video signals based on a discrimination result of the signal discriminating circuit. The driver logic circuit drives a first display panel based on the first video signal. The second interface unit converts the second video signal into a second signal and provides the second signal through a second interface to an external display device. The synchronization processing unit receives a synchronization signal from the external display device and provides the synchronization signal to the host.

Abstract: A display driver includes a first interface controller, a signal selector, a driver logic unit and a second interface controller. The first interface controller processes a control command transferred through a first interface mode to provide a path control command and a panel control command. The signal selector receives the path control command from the first interface controller, and separates a first video signal and a second video signal from a video signal conforming to a video interface mode. The driver logic unit receives the first video signal from the signal selector and the panel control command from the first interface controller to drive a display panel. The second interface controller outputs the second video signal device through a second interface mode to an external.

Abstract: A device for data compression includes a domain transformer unit, a classifying unit, a variable length encoder, a fixed length encoder and a memory unit. The domain transformer unit transforms time-domain data into frequency-domain data. The classifying unit determines an encoding type of the frequency-domain data based on occurrence probability of the frequency-domain data. The variable length encoder encodes first frequency-domain data that are determined to be encoded by variable length coding. The fixed length encoder encodes second frequency-domain data that are determined to be encoded by fixed length coding. The memory unit stores the encoded first and second frequency-domain data by relocating the encoded first and second frequency-domain data such that the encoded first frequency-domain data are placed adjacently and the encoded second frequency-domain data are placed adjacently. Therefore, the time for decoding the corresponding data may be reduced.

Abstract: A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.