Patents by Inventor Jong Shik Yoon
Jong Shik Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220238689Abstract: An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction.Type: ApplicationFiled: September 3, 2021Publication date: July 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Changseop YOON, Jong Shik YOON
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Patent number: 9922979Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.Type: GrantFiled: February 3, 2016Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yup Chung, Jong-shik Yoon, Hwa-sung Rhee, Hee-don Jeong, Je-Min Yoo, Kyu-man Cha, Jong-mil Youn, Hyun-jo Kim
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Patent number: 9754789Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.Type: GrantFiled: October 8, 2014Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee, Byung-Sung Kim
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Publication number: 20160284706Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.Type: ApplicationFiled: February 3, 2016Publication date: September 29, 2016Inventors: Jae-yup CHUNG, Jong-shik YOON, Hwa-sung RHEE, Hee-don JEONG, Je-Min YOO, Kyu-man CHA, Jong-mil YOUN, Hyun-jo KIM
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Patent number: 9425148Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.Type: GrantFiled: December 18, 2012Date of Patent: August 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jun Kim, Hae-Wang Lee, Chul-Hong Park, Dong-Kyun Sohn, Jong-Shik Yoon
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Patent number: 9412693Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.Type: GrantFiled: February 6, 2014Date of Patent: August 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee
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Patent number: 9209177Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.Type: GrantFiled: March 4, 2013Date of Patent: December 8, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Young-Gun Ko
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Publication number: 20150111381Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.Type: ApplicationFiled: October 8, 2014Publication date: April 23, 2015Inventors: Yoon-Hae KIM, Jong-Shik YOON, Hwa-Sung RHEE, Byung-Sung KIM
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Patent number: 8952452Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.Type: GrantFiled: December 3, 2012Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
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Publication number: 20140332871Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.Type: ApplicationFiled: February 6, 2014Publication date: November 13, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee
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Publication number: 20140203362Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.Type: ApplicationFiled: March 4, 2013Publication date: July 24, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae KIM, Jong-Shik YOON, Young-Gun KO
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Publication number: 20130248990Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.Type: ApplicationFiled: December 18, 2012Publication date: September 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jun KIM, Hae-Wang LEE, Chul-Hong PARK, Dong-Kyun SOHN, Jong-Shik YOON
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Publication number: 20130248950Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.Type: ApplicationFiled: December 3, 2012Publication date: September 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-Seong KANG, Yoon-Hae KIM, Jong-Shik YOON
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Patent number: 7811893Abstract: The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300) for constructing an integrated circuit.Type: GrantFiled: June 22, 2009Date of Patent: October 12, 2010Assignee: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Andrew Tae Kim
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Patent number: 7795085Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.Type: GrantFiled: June 12, 2006Date of Patent: September 14, 2010
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Publication number: 20090258468Abstract: The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300 ) for constructing an integrated circuit.Type: ApplicationFiled: June 22, 2009Publication date: October 15, 2009Applicant: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Andrew Tae Kim
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Patent number: 7514331Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.Type: GrantFiled: June 8, 2006Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Amitava Chatterjee, Haowen Bu
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Publication number: 20070287239Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.Type: ApplicationFiled: June 12, 2006Publication date: December 13, 2007
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Publication number: 20070287258Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.Type: ApplicationFiled: June 8, 2006Publication date: December 13, 2007Applicant: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Amitava Chatterjee, Haowen Bu
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Patent number: 7229869Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).Type: GrantFiled: March 8, 2005Date of Patent: June 12, 2007Assignee: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian E. Goodlin, Karen H. R. Kirmse