Abstract: An image sensor has multiple blocks each with multiple pixels; each block uses a separate analog-to-digital converter (ADC). The ADCs feed digitized images into an image DRAM, and the image DRAM feeds digitized images to an alignment buffer in turn providing images to an image processor. The ADCs feed digitized image data into the image DRAM in hyperlong words, using staggered, overlapping, word lines to write each hyperlong word. A method of imaging includes exposing a photosensor array to light, reading pixels of the array in sequence within each block of pixels, one pixel in each block simultaneously; and digitizing pixels in separate ADCs for each block. Digitized pixels are written to image DRAM as hyperlong words with one pixel from each block in parallel using staggered, overlapping, word lines. Pixels are read from the image DRAM into an alignment buffer and thence to the image processor.

Abstract: An image sensor has multiple blocks each with multiple pixels; each block uses a separate analog-to-digital converter (ADC). The ADCs feed digitized images into an image DRAM, and the image DRAM feeds digitized images to an alignment buffer in turn providing images to an image processor. The ADCs feed digitized image data into the image DRAM in hyperlong words, using staggered, overlapping, word lines to write each hyperlong word. A method of imaging includes exposing a photosensor array to light, reading pixels of the array in sequence within each block of pixels, one pixel in each block simultaneously; and digitizing pixels in separate ADCs for each block. Digitized pixels are written to image DRAM as hyperlong words with one pixel from each block in parallel using staggered, overlapping, word lines. Pixels are read from the image DRAM into an alignment buffer and thence to the image processor.

Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data.

Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: A dynamic random access memory (DRAM) including a plurality of memory banks is capable of selectively performing a self-refresh operation with respect to only a subset of the banks. The DRAM includes a plurality of row decoders for selecting word lines of the memory cells of the memory banks, an address generator for generating internal addresses which sequentially vary during a self-refresh mode, a refresh bank designating circuit for generating refresh bank designating signals for designating a memory bank to be refreshed, and a bank selection decoder for designating one or more memory banks to be refreshed by the refresh bank designating signals and supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the information of the internal addresses. The self-refresh operation is performed for only selected memory banks, or alternatively, only in those memory banks in which data is stored, thereby minimizing power consumption.

Abstract: A dynamic random access memory (DRAM) including a plurality of memory banks is capable of selectively performing a self-refresh operation with respect to only a subset of the banks. The DRAM includes a plurality of row decoders for selecting word lines of the memory cells of the memory banks, an address generator for generating internal addresses which sequentially vary during a self-refresh mode, a refresh bank designating circuit for generating refresh bank designating signals for designating a memory bank to be refreshed, and a bank selection decoder for designating one or more memory banks to be refreshed by the refresh bank designating signals and supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the information of the internal addresses. The self-refresh operation is performed for only selected memory banks, or alternatively, only in those memory banks in which data is stored, thereby minimizing power consumption.