Abstract: A memory controller includes a read operation controller, an error correction circuit, and a read voltage controller. The read operation controller controls a memory device to read pieces of data from a selected page of the memory device by read voltages having different levels. The error correction circuit determines fail bit numbers of the pieces of data. The read voltage controller selects a reference voltage variation from among voltage variations included in a first read voltage table, based on an erase write cycle count of the memory device, and a reference fail bit number indicating a largest fail bit number of the fail bit numbers, and adjusts a level of each of the read voltages based on the reference voltage variation and a ratio value of a corresponding one of the fail bit numbers to the reference fail bit number.

Abstract: A memory controller includes a read operation controller, an error correction circuit, and a read voltage controller. The read operation controller controls a memory device to read pieces of data from a selected page of the memory device by read voltages having different levels. The error correction circuit determines fail bit numbers of the pieces of data. The read voltage controller selects a reference voltage variation from among voltage variations included in a first read voltage table, based on an erase write cycle count of the memory device, and a reference fail bit number indicating a largest fail bit number of the fail bit numbers, and adjusts a level of each of the read voltages based on the reference voltage variation and a ratio value of a corresponding one of the fail bit numbers to the reference fail bit number.

Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.

Abstract: A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.

Abstract: In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program.

Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.

Abstract: A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.

Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.

Abstract: A semiconductor memory device and a method of operating same includes reading a number of program/erase operations stored in a program/erase number storage unit, setting a pulse width of a program voltage based on the read number of program/erase operations, and performing a program operation on memory cells using the program voltage having the set pulse width. Setting of the pulse width of the program voltage includes decreasing the pulse width of the program voltage as the number of program/erase operations increases.

Abstract: A semiconductor memory device and a method of operating same includes reading a number of program/erase operations stored in a program/erase number storage unit, setting a pulse width of a program voltage based on the read number of program/erase operations, and performing a program operation on memory cells using the program voltage having the set pulse width. Setting of the pulse width of the program voltage includes decreasing the pulse width of the program voltage as the number of program/erase operations increases.

Abstract: In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program.

Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.

Abstract: A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor and the memory cell adjacent to the source selection transistor and between the drain selection transistor and the memory cell adjacent to the drain selection transistor, prevents the memory cell adjacent to the source or drain selection transistor from being degraded in programming speed due to program disturbance.

Abstract: A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.