Patents by Inventor Jong-Sung Jeon
Jong-Sung Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128484Abstract: A fuel cell system and a method of controlling the system are provided. The fuel cell system includes: a fuel cell having a plurality of cells to generate power through a reaction between hydrogen supplied to an anode space and oxygen supplied to a cathode space; a power storage device to be charged with power generated by the fuel cell or discharged to supply power; and a controller. The controller recirculates hydrogen, diffused from the anode space to the cathode space, into the anode space by supplying power charged in the power storage device to the fuel cell when the power generation of the fuel cell is stopped. The controller is configured to control whether to supply the power to the fuel cell based on a pressure measured in the anode space and voltages of the cells that constitute the fuel cell.Type: ApplicationFiled: April 18, 2023Publication date: April 18, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hoon Ryu, Jae Sung Ryu, Jong Hyun Lee, Yei Sik Jeon, Young Wook Cheong
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Publication number: 20230410865Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.Type: ApplicationFiled: January 30, 2023Publication date: December 21, 2023Inventors: Jiefang DENG, WEI CHANG, Huihui LI, Xiang LIU, JONG SUNG JEON
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Patent number: 10985180Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: GrantFiled: February 27, 2020Date of Patent: April 20, 2021Assignee: SK hynix Inc.Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
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Publication number: 20200203375Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventors: Jong Sung JEON, Eun Mee KWON, Da Som LEE, Bong Hoon LEE
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Patent number: 10615175Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: GrantFiled: July 9, 2019Date of Patent: April 7, 2020Assignee: SK hynix Inc.Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
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Publication number: 20190333936Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Jong Sung JEON, Eun Mee KWON, Da Som LEE, Bong Hoon LEE
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Patent number: 10396095Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: GrantFiled: July 5, 2018Date of Patent: August 27, 2019Assignee: SK hynix Inc.Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
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Patent number: 10318678Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.Type: GrantFiled: April 16, 2014Date of Patent: June 11, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook Lee, Han-Gu Kim, Young-Keun Lee, Jong-Sung Jeon
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Publication number: 20190115364Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.Type: ApplicationFiled: July 5, 2018Publication date: April 18, 2019Inventors: Jong Sung JEON, Eun Mee KWON, Da Som LEE, Bong Hoon LEE
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Patent number: 10186505Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.Type: GrantFiled: May 24, 2017Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hyun Yoo, Jin-Tae Kim, Jong-Sung Jeon
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Patent number: 10056479Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.Type: GrantFiled: January 12, 2016Date of Patent: August 21, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Yoo, Jin-Hyun Noh, Kee-Moon Chun, Jong-Sung Jeon
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Patent number: 9935167Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.Type: GrantFiled: September 19, 2016Date of Patent: April 3, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyun Noh, Su-Tae Kim, Jae-Hyun Yoo, Byeong-Ryeol Lee, Jong-Sung Jeon
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Publication number: 20170256533Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.Type: ApplicationFiled: May 24, 2017Publication date: September 7, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun YOO, Jin-Tae KIM, Jong-Sung JEON
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Patent number: 9679886Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.Type: GrantFiled: October 8, 2014Date of Patent: June 13, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hyun Yoo, Jin-Tae Kim, Jong-Sung Jeon
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Patent number: 9548401Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.Type: GrantFiled: April 29, 2015Date of Patent: January 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Yoo, Jin-Hyun Noh, Su-Tae Kim, Byeong-Ryeol Lee, Seong-Hun Jang, Jong-Sung Jeon
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Publication number: 20170005162Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-Hyun NOH, Su-Tae KIM, Jae-Hyun YOO, Byeong-Ryeol LEE, Jong-Sung JEON
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Publication number: 20160372456Abstract: A semiconductor device includes a first well in a substrate, a gate structure on the first well, a second well below the gate structure in the first well, a third well in a first side of the gate structure and in the first well to be adjacent to the second well, the third well having a conductivity type different from that of the second well, a fourth well overlapped with the third well, a fifth well in a second side of the gate structure and in the second well, a sixth well below the gate structure and in the second well, the sixth well being adjacent to the fifth well and having an impurity concentration higher than the impurity concentration of the second well, and a first device isolation layer overlapped with the second well and disposed farther away from the gate structure than the fifth well.Type: ApplicationFiled: May 16, 2016Publication date: December 22, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Yoo, Jong-Sung JEON
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Patent number: 9472659Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.Type: GrantFiled: July 30, 2015Date of Patent: October 18, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyun Noh, Su-Tae Kim, Jae-Hyun Yoo, Byeong-Ryeol Lee, Jong-Sung Jeon
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Publication number: 20160225896Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.Type: ApplicationFiled: January 12, 2016Publication date: August 4, 2016Inventors: Jae-Hyun YOO, Jin-Hyun NOH, Kee-Moon CHUN, Jong-Sung JEON
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Publication number: 20160149057Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.Type: ApplicationFiled: April 29, 2015Publication date: May 26, 2016Inventors: JAE-HYUN YOO, JIN-HYUN NOH, SU-TAE KIM, BYEONG-RYEOL LEE, SEONG-HUN JANG, JONG-SUNG JEON