Abstract: An energy storage module includes: a plurality of battery cells arranged in a first direction such that long side surfaces of adjacent ones of the battery cells face one another; a plurality of insulation spacers, at least one of the insulation spacers being between each adjacent pair of the battery cells, each of the insulation spacers including a heat-insulating first sheet and a plurality of flame-retardant second sheets respectively adhered to opposite surfaces of the first sheet by an adhesion member; a cover member including an internal receiving space configured to accommodate the battery cells and the insulation spacers; a top plate coupled to the cover member, the top plate including ducts respectively corresponding to vents of the battery cells and having fire extinguishing agent openings respectively corresponding to the insulation spacers; a top cover coupled to the top plate and having discharge openings respectively corresponding to the ducts; and an extinguisher sheet between the top cover and

Abstract: An energy storage module includes: a cover member accommodating a plurality of battery cells in an internal receiving space, each of the battery cells including a vent; a top plate coupled to a top of the cover member and including a duct corresponding to the vent of at least one of the battery cells; a top cover coupled to a top of the top plate and having an exhaust area corresponding to the duct, the exhaust area having a plurality of discharge openings, the top cover including a protrusion protruding from a bottom surface of the top cover, the protrusion extending around a periphery of the exhaust area and around a distal end of the duct; and an extinguisher sheet between the top cover and the top plate, the extinguisher sheet being configured to emit a fire extinguishing agent at a reference temperature.

Abstract: A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.

Abstract: Provided is a semiconductor device. The semiconductor device includes a floating gate disposed on a substrate; a memory gate disposed on the floating gate; a first spacer disposed sidewalls of the floating gate and the memory gate, and an upper surface of the substrate; a second spacer disposed on the first spacer; a select high-k film disposed on a first portion of a sidewall of the first spacer between the substrate and the second spacer; and a select gate disposed on a second portion of the sidewall of the first spacer between the substrate and the second spacer. A width of a portion of the first spacer is reduced as a distance to the substrate decreases, and the portion of the first spacer is disposed between the substrate and the second spacer.

Abstract: A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.