Patents by Inventor Jong Tae Baek

Jong Tae Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112864
    Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.
    Type: Application
    Filed: July 10, 2023
    Publication date: April 4, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong PARK, Jung Tae PARK, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Jung Jin PARK, Rak Hyeon BAEK, Sun Mi KIM, Yong Ung LEE
  • Publication number: 20170021204
    Abstract: An oxygen respirator is provided for emergency evacuations, which is simple to carry. The oxygen respirator increases the amount of air which a user can breathe by reusing the expirations of the user, such that the survival rate of the user is increased.
    Type: Application
    Filed: November 29, 2013
    Publication date: January 26, 2017
    Applicant: CIJ
    Inventor: Jong Tae BAEK
  • Publication number: 20150056905
    Abstract: Oxygen supply elevator which supplies oxygen to an internal space of the elevator or a separate oxygen mask provided in the elevator, thereby allowing a user to easily breathe and removing smoke or the like. The oxygen supply elevator includes: an oxygen containing unit which is provided in a facility mounting space formed on the elevator and contains oxygen at pressure higher than atmospheric pressure; an oxygen supply unit which is connected with the oxygen containing unit through at least one communication channel and supplies oxygen to an oxygen supply space in the elevator; a valve unit which is provided on the communication channel and adjusts a flow rate of oxygen discharged from the oxygen containing unit; and a control unit which is connected to the valve unit and adjusts whether to open or close the valve unit or an opening amount of the valve unit.
    Type: Application
    Filed: March 18, 2013
    Publication date: February 26, 2015
    Applicant: CIJ CO., LTD.
    Inventor: Jong Tae Baek
  • Publication number: 20130042861
    Abstract: Provided is a helmet-type personal disaster relief device which supplies fresh air to a wearer during an evacuation time period upon the occurrence of disasters, and protects the skin of the face, neck and shoulders of the wearer. For this purpose, the helmet-type personal disaster relief device of the present invention comprises a helmet body having an outer shell, an inner shell formed inside the outer shell, and an air storage space formed between the outer shell and the inner shell.
    Type: Application
    Filed: April 26, 2011
    Publication date: February 21, 2013
    Applicant: CIJ CORPORATION
    Inventor: Jong-tae Baek
  • Publication number: 20120312585
    Abstract: There is provided a soft electrode material including an electrode layer containing a mixture of carbon black and at least one selected from carbon nanotube and graphene, so that the soft electrode material can facilitate various transformation thereof in response to physical transformation of an electrode, such as warpage, elongation, and the like; prevent the rapid reduction in electric conductivity of an electrode while maintaining flexibility and elasticity of the electrode at the time of the transformation; and provide excellent reliability, and thus, electrical-mechanical energy conversion efficiency of a soft electronic component such as an actuator including the soft electrode material, can be increased, and electric conductivity of the electrode layer can be improved as the electrical-mechanical conversion efficiency increases.
    Type: Application
    Filed: February 24, 2011
    Publication date: December 13, 2012
    Applicant: CIJ. CO., LTD.
    Inventors: Jong Tae Baek, Moon Pyung Park, Hyung-Ho Park, Hyuncheol Kim, Jin-Seok Lee
  • Patent number: 6292084
    Abstract: A fine inductor having a 3-dimensional coil structure is disclosed. The inductor includes an insulating layer having a groove, a plurality of first conductive patterns wherein the respective first conductive patterns cover bottom and both walls of the groove formed in the insulating layer, both ends of the respective first conductive patterns are extended over upper surface of both sides of the groove, and each of the first conductive patterns is disposed at a predetermined space between adjacent first conductive patterns, and a plurality of second conductive patterns wherein one ends of the respective second conductive patterns are connected to the one ends of the first conductive patterns extended over upper surface and the other ends of the respective second conductive patterns are connected to the other ends of the adjacent first conductive patterns extended over upper surface, thereby forming a coil structure together with the first conductive patterns.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: September 18, 2001
    Assignee: Electronics and Telecommunication Research Institute
    Inventors: Chang Auck Choi, Jong Hyun Lee, Won Ick Jang, Yong Il Lee, Jong Tae Baek, Hyung Joun Yoo
  • Patent number: 6165555
    Abstract: A chemical vapor deposition apparatus and a copper film formation method are disclosed. The chemical vapor deposition apparatus includes a process gas delivery unit including a first storing unit using a liquid deposition source, a delivery unit for transferring a liquid deposition source in the first storing unit to an evaporator, and an evaporator for vaporizing the liquid deposition source transferred from the delivery unit and supplying a process gas; and a reaction chamber for receiving the process gas from the process gas delivery unit and deposition a predetermined thin film on a wafer or substrate mounted therein.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: December 26, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon Jun, Youn Tae Kim, Jong Tae Baek
  • Patent number: 6084656
    Abstract: This invention discloses a programmable mask for exposure apparatus which is formed by an integrated pixels of a micro-devices which shut or open a light by an electrical signal. This invention provides a photolithography method by projecting on a silicon wafer a directly designed circuit pattern which is made on a programmable mask fabricated by an integration of many a micro optical shutter devices as a pixels.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: July 4, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Auck Choi, Jong Hyun Lee, Won Ick Jang, Yong Il Lee, Jong Tae Baek, Bo Woo Kim
  • Patent number: 6069073
    Abstract: An improved method for forming diffusion barrier layers for sub-micron connects in integrated circuits is disclosed. The dual diffusion barriers is easily formed according to two-step annealing processes. The anneal includes two anneal cycles or steps, each cycle is performed at a separate and distinct temperature cycles. Each cycle is performed in the presence of ammonia (NH3) or nitrogen ambient. As a result of the first low-temperature cycle, a nitridation occurs at the upper surface to form a binary diffusion barrier layer. As a result of the second high-temperature cycle, an out-diffusion of silicon ions occurs at the lower surface to form a ternary alloys. The dual diffusion barriers obtained by a simple and easy two-step anneal processing exhibits an improved barrier performance. Furthermore, it is possible to form highly stable multilevel interconnections without any deterioration problems by reducing the sophisticated processing steps.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: May 30, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Youn Tae Kim, Chi Hoon Jun, Jong Tae Baek
  • Patent number: 6066554
    Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Youn Tae Kim, Chi Hoon Jun, Jong Tae Baek
  • Patent number: 5885898
    Abstract: The present invention relates to a method for forming a diffusion barrier layer, the method comprising the steps of: forming an insulation membrane having an opening for exposing a diffusion region to a silicon substrate formed with the diffusion region of a predetermined conductivity; vacuum-evaporating a metal of high melting point to surface and sides of the insulation membrane and to an upper area of the diffusion region, to thereby form a metal layer; and forming on the metal layer a low resistance layer and a diffusion barrier layer according to first and second quick heating treatment steps under nitric or ammoniac atmosphere. Accordingly, the low resistance layer can be thinned out while the diffusion prevention layer can be quickly formed to thereby improve diffusion prevention characteristic and to reduce stress from an interface with the semiconductor substrate.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: March 23, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Youn-Tae Kim, Chi-Hoon Jun, Jong-Tae Baek
  • Patent number: 5843837
    Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: December 1, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Tae Baek, Youn-Tae Kim, Hyung-Joun Yoo
  • Patent number: 5789796
    Abstract: The present invention relates to a technology of an electrically programmable anti-fuse device. The anti-fuse device comprises a semiconductor substrate provided with a plurality of functional elements; a field oxide layer formed on said semiconductor substrate, for electrically isolating the functional elements from each other; a predetermined pattern of a first electrode formed on said field oxide layer; a first insulating layer having two contact holes isolated from each other only on said first electrode, deposited on said field oxide layer as well as both end portions and center portion of said first electrode; a second insulating layer formed in said contact holes, to serves as an interlayer; and a second electrode formed on said second insulating layer.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: August 4, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang-Won Kang, Jong-Tae Baek