Abstract: A test device includes a test mounting circuit having a plurality of semiconductor devices mounted thereon as respective devices-under-test. Each device-under-test includes a corresponding delay control circuit and a target circuit therein. Test logic is provided, which is electrically coupled to the test mounting circuit. The test logic is configured to generate a test input(s), which is provided in parallel to the delay control circuits within the plurality of devices-under-test. The delay control circuits include at least first and second delay control circuits, which are configured to pass the test input(s) to corresponding first and second target circuits during respective first and second test time intervals that are out-of-phase relative to each other in order to achieve more uniform power consumption requirements of the test mounting circuit during testing.

Abstract: A dual band wireless power reception unit is disclosed. The wireless power reception unit according to one embodiment comprises: a first resonator; a second resonator connected to the first resonator in parallel; a single rectifier having, as an input, a node in which outputs of the first resonator and the second resonator are connected to each other in parallel; at least one switch having a first output, a second output, and an input, wherein the second output is connected to the ground; at least one capacitor connected to the second resonator in parallel, and of which one terminal is connected to the first output of the switch and the other terminal is connected to the rectifier input; and a frequency sensor sensing an input frequency from the rectifier input, and of which an output is connected to the input of the switch.

Abstract: A test device includes a test mounting circuit having a plurality of semiconductor devices mounted thereon as respective devices-under-test. Each device-under-test includes a corresponding delay control circuit and a target circuit therein. Test logic is provided, which is electrically coupled to the test mounting circuit. The test logic is configured to generate a test input(s), which is provided in parallel to the delay control circuits within the plurality of devices-under-test. The delay control circuits include at least first and second delay control circuits, which are configured to pass the test input(s) to corresponding first and second target circuits during respective first and second test time intervals that are out-of-phase relative to each other in order to achieve more uniform power consumption requirements of the test mounting circuit during testing.

Abstract: A magnetic resonance wireless power transmission device capable of adjusting resonance frequency is disclosed. A wireless power transmission device according to an embodiment of the present invention comprises: a power amplifier for amplifying a wireless power signal using a driving frequency signal; a resonator for configuring a resonance tank and wirelessly transmitting, through magnetic resonance, the wireless power signal output from the power amplifier using a resonance frequency of the resonance tank; and a resonance control unit for controlling a duty ratio using a frequency applied to the resonator or a frequency signal generated by the resonator and adjusting the resonance frequency of the resonator.

Abstract: A dual band wireless power reception unit is disclosed. The wireless power reception unit according to one embodiment comprises: a first resonator; a second resonator connected to the first resonator in parallel; a single rectifier having, as an input, a node in which outputs of the first resonator and the second resonator are connected to each other in parallel; at least one switch having a first output, a second output, and an input, wherein the second output is connected to the ground; at least one capacitor connected to the second resonator in parallel, and of which one terminal is connected to the first output of the switch and the other terminal is connected to the rectifier input; and a frequency sensor sensing an input frequency from the rectifier input, and of which an output is connected to the input of the switch.

Abstract: An active diode having an improved transistor turn-off control method is disclosed. The active diode comprises: a comparator for comparing voltages of both ends of a parasitic diode of a transistor; and a gate driver for controlling a gate terminal of the transistor according to the comparison result of the comparator, and estimates a turn-on time of the transistor and uses the same to control the gate terminal of the transistor.

Abstract: A magnetic resonance wireless power transmission device capable of adjusting resonance frequency is disclosed. A wireless power transmission device according to an embodiment of the present invention comprises: a power amplifier for amplifying a wireless power signal using a driving frequency signal; a resonator for configuring a resonance tank and wirelessly transmitting, through magnetic resonance, the wireless power signal output from the power amplifier using a resonance frequency of the resonance tank; and a resonance control unit for controlling a duty ratio using a frequency applied to the resonator or a frequency signal generated by the resonator and adjusting the resonance frequency of the resonator.

Abstract: An active diode having an improved transistor turn-off control method is disclosed. The active diode comprises: a comparator for comparing voltages of both ends of a parasitic diode of a transistor; and a gate driver for controlling a gate terminal of the transistor according to the comparison result of the comparator, and estimates a turn-on time of the transistor and uses the same to control the gate terminal of the transistor.

Abstract: An active diode driver for operating a switch of an active rectifier using an active diode is provided. The active diode driver may first control a soft turn-on of the switch and secondly control a hard turn-on of the switch, thereby making it possible for the switch to be softly turned-on.

Abstract: An active diode that features improved control of transistor turn-off is provided. Such an active diode may include a comparator to compare voltages between opposite ends of a parasitic diode, and a gate driver to control a gate terminal of the transistor according to the comparison result of the comparator. Furthermore, the active diode may further include an off-timing controller to control the transistor to be turned off at a point in time when voltages of the opposite ends of the parasitic diode turn positive. Thus, the active diode may be turned off when required.

Abstract: A gate driver driving a switching device is disclosed. The gate driver includes a capacitor which is coupled to the input of the switching device. The gate drive power consumption is reduced by this additional capacitor.

Abstract: An active diode that features improved control of transistor turn-off is provided. Such an active diode may include a comparator to compare voltages between opposite ends of a parasitic diode, and a gate driver to control a gate terminal of the transistor according to the comparison result of the comparator. Furthermore, the active diode may further include an off-timing controller to control the transistor to be turned off at a point in time when voltages of the opposite ends of the parasitic diode turn positive. Thus, the active diode may be turned off when required.

Abstract: A gate driver driving a switching device is disclosed. The gate driver includes a capacitor which is coupled to the input of the switching device. The gate drive power consumption is reduced by this additional capacitor.

Abstract: An active diode driver for operating a switch of an active rectifier using an active diode is provided. The active diode driver may first control a soft turn-on of the switch and secondly control a hard turn-on of the switch, thereby making it possible for the switch to be softly turned-on.

Abstract: The present invention relates to a power factor correction circuit and a method of driving the power factor correction circuit. The power factor correction circuit according to the present invention includes a power transfer element configured to receive an input voltage, an input current corresponding to the input voltage flowing through the power transfer element, and a switch connected to the power transfer element and configured to control an output voltage generated by the current flowing through the power transfer element.

Abstract: An apparatus configured to generate control data. The apparatus includes a counter unit configured to receive an input signal having a first state and a second state and counts the first state in the input signal, a delay unit configured to delay the count value for a predetermined time, and a data output unit configured to receive the delayed count value from the counter unit and then generate the control data based on the delayed count value.

Abstract: Disclosed are a switch controller, a switch control method, and a converter based thereon. The switch controller generates an input sensing voltage corresponding to the input voltage of the converter, and compares the input sensing voltage with a predetermined first reference value. The switch controller generates a zero cross detection signal with a first level or a second level depending upon the comparison result, and generates a reference clock signal varying in frequency in accordance with one cycle of the zero cross detection signal. The switch controller generates digital signals by using the reference clock signal and the zero cross detection signal. The digital signals synchronize with the zero cross detection signal, and increase in accordance with the reference clock signal during a half of one cycle of the zero cross detection signal, while decreasing in accordance with the reference clock signal during the other half cycle of the zero cross detection signal.

Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: The present invention relates to a power factor correction circuit and a method of driving the power factor correction circuit. The power factor correction circuit according to the present invention includes a power transfer element configured to receive an input voltage, an input current corresponding to the input voltage flowing through the power transfer element, and a switch connected to the power transfer element and configured to control an output voltage generated by the current flowing through the power transfer element.

Abstract: Disclosed are a switch controller, a switch control method, and a converter based thereon. The switch controller generates an input sensing voltage corresponding to the input voltage of the converter, and compares the input sensing voltage with a predetermined first reference value. The switch controller generates a zero cross detection signal with a first level or a second level depending upon the comparison result, and generates a reference clock signal varying in frequency in accordance with one cycle of the zero cross detection signal. The switch controller generates digital signals by using the reference clock signal and the zero cross detection signal. The digital signals synchronize with the zero cross detection signal, and increase in accordance with the reference clock signal during a half of one cycle of the zero cross detection signal, while decreasing in accordance with the reference clock signal during the other half cycle of the zero cross detection signal.