Patents by Inventor Jong Ung BAEK
Jong Ung BAEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240112864Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.Type: ApplicationFiled: July 10, 2023Publication date: April 4, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong PARK, Jung Tae PARK, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Jung Jin PARK, Rak Hyeon BAEK, Sun Mi KIM, Yong Ung LEE
-
Patent number: 11296276Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.Type: GrantFiled: November 19, 2019Date of Patent: April 5, 2022Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Jong Ung Baek, Kei Ashiba, Jin Young Choi, Mi Ri Park, Hyun Gyu Lee, Han Sol Jun, Sun Hwa Jung
-
Publication number: 20220076108Abstract: The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a two-terminal spin device for performing integration and fire, and the two-terminal spin device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.Type: ApplicationFiled: November 7, 2019Publication date: March 10, 2022Applicant: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Jea Gun PARK, Jong Ung BAEK
-
Publication number: 20220013714Abstract: Disclosed is a memory device including a lower electrode, a seed layer, a synthetic antiferromagnetic layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate, wherein the magnetic tunnel junction includes a pinned layer, a tunnel barrier layer, and free layers, wherein the free layers include a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order.Type: ApplicationFiled: October 24, 2019Publication date: January 13, 2022Applicant: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Jea Gun PARK, Jong Ung BAEK
-
Patent number: 11133458Abstract: Disclosed is a memory device. A memory device according to an embodiment of the present invention includes a memory device including a substrate; and a lower electrode, seed layer, lower synthetic antiferromagnetic layer, magnetic tunnel junction, upper synthetic antiferromagnetic layer, and upper electrode that are laminated on the substrate, wherein the magnetic tunnel junction includes a lower pinned layer, lower tunnel barrier layer, lower free layer, separation layer, upper free layer, upper tunnel barrier layer and upper pinned layer that are sequentially laminated.Type: GrantFiled: January 4, 2019Date of Patent: September 28, 2021Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Jin Young Choi, Han Sol Jun, Dong Gi Lee, Kondo Kei, Jong Ung Baek
-
Patent number: 11050014Abstract: A memory device contains lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode, which are formed on a substrate in a laminated manner. In the memory device, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: June 29, 2021Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
-
Publication number: 20210135091Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.Type: ApplicationFiled: November 19, 2019Publication date: May 6, 2021Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Jong Ung BAEK, Kei ASHIBA, Jin Young CHOI, Mi Ri PARK, Hyun Gyu LEE, Han Sol JUN, Sun Hwa JUNG
-
Publication number: 20200350489Abstract: Disclosed is a memory device. A memory device according to an embodiment of the present invention includes a memory device including a substrate; and a lower electrode, seed layer, lower synthetic antiferromagnetic layer, magnetic tunnel junction, upper synthetic antiferromagnetic layer, and upper electrode that are laminated on the substrate, wherein the magnetic tunnel junction includes a lower pinned layer, lower tunnel barrier layer, lower free layer, separation layer, upper free layer, upper tunnel barrier layer and upper pinned layer that are sequentially laminated.Type: ApplicationFiled: January 4, 2019Publication date: November 5, 2020Applicant: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Jea Gun PARK, Jin Young CHOI, Han Sol JUN, Dong Gi LEE, Kondo KEI, Jong Ung BAEK
-
Publication number: 20200266333Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: ApplicationFiled: March 18, 2015Publication date: August 20, 2020Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong LEE, Seung Eun LEE, Min Su JEON, Jong Ung BAEK, Tae Hun SHIM
-
Patent number: 10586919Abstract: A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: March 10, 2020Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
-
Patent number: 10516097Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: GrantFiled: March 18, 2015Date of Patent: December 24, 2019Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee, Min Su Jeon, Jong Ung Baek, Tae Hun Shim
-
Publication number: 20190229259Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: ApplicationFiled: March 18, 2015Publication date: July 25, 2019Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong LEE, Seung Eun LEE, Min Su JEON, Jong Ung BAEK, Tae Hun SHIM
-
Publication number: 20190172997Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.Type: ApplicationFiled: March 18, 2015Publication date: June 6, 2019Applicant: Industry-University Cooperation Foundation Hanyang UniversityInventors: Jea Gun PARK, Du Yeong LEE, Seung Eun LEE, Min Su JEON, Jong Ung BAEK, Tae Hun SHIM