Abstract: A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arranged and a peripheral circuit region for driving the memory cells. The memory cells comprise a first conductivity type semiconductor substrate, second conductivity type source and drain regions separated from each other with a channel region therebetween on the main surface of the semiconductor substrate, a gate oxide film formed on the upper portion of the channel region, a floating gate formed on the gate oxide film, an interlayer dielectric film formed on the upper portion of the floating gate, a control gate formed on the interlayer dielectric film, and a bird's beak area formed between the source/drain regions and the floating gate having greater thickness than the gate oxide film.

Abstract: A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arranged and a peripheral circuit region for driving the memory cells. The memory cells comprise a first conductivity type semiconductor substrate, second conductivity type source and drain regions separated from each other with a channel region therebetween on the main surface of the semiconductor substrate, a gate oxide film formed on the upper portion of the channel region, a floating gate formed on the gate oxide film, an interlayer dielectric film formed on the upper portion of the floating gate, a control gate formed on the interlayer dielectric film, and a bird's beak area formed between the source/drain regions and the floating gate having greater thickness than the gate oxide film.

Abstract: There is provided a method for designing a cell array layout of a non-volatile memory device which facilitates a contact hole process and contributes to the reduction of chip size, by modifying a layout of active contact holes. In the method, the distance between active regions are uniformly maintained in all cells by forming a second active line over a active contact region. Therefore, variations, caused by microloading effects when patterning active regions, of the width of active regions in some cell strings can be prevented. Operational failure of a cell caused by variations in the coupling ratio can be prevented, as well.

Abstract: A highly integrated flash memory device having a stable cell is provided.

Abstract: Nonvolatile memory devices include a substrate, and an array of field isolation regions in the substrate. The array of field isolation regions define a plurality of spaced apart first active regions in the substrate, which extend along the substrate in a first direction. The array of field isolation regions also define a plurality of spaced apart second active regions in the substrate, which extend along the substrate in a second direction which is orthogonal to the first direction. An array of floating gate isolation regions is also provided. A respective one of the floating gate isolation regions is on a respective one of the array of field isolation regions. The floating gate isolation regions extend on the corresponding field isolation region along the first direction. The array of floating gate isolation regions can prevent damage to the substrate when the floating gate is defined using the control gate as a mask.