Abstract: A display device includes: a display panel including pixels connected to compensation gate lines, and a compensation gate driver which supplies compensation gate signals to the display panel. The compensation gate driver includes: a first compensation gate driver which generates the compensation gate signals based on a first-first clock signal and a second-first clock signal and a second compensation gate driver which generates the compensation gate signals based on a first-second clock signal and a second-second clock signal. The first-first clock signal and the second-first clock signal have the same waveform as the first-second clock signal and the second-second clock signal, respectively, during a scan period in which a compensation gate signal is supplied to the display panel, and have different waveforms from the first-second clock signal and the second-second clock signal, respectively, during a blank period in which the compensation gate signal is not supplied to the display panel.

Abstract: A display device includes: a display panel including pixels connected to compensation gate lines, and a compensation gate driver which supplies compensation gate signals to the display panel. The compensation gate driver includes: a first compensation gate driver which generates the compensation gate signals based on a first-first clock signal and a second-first clock signal and a second compensation gate driver which generates the compensation gate signals based on a first-second clock signal and a second-second clock signal. The first-first clock signal and the second-first clock signal have the same waveform as the first-second clock signal and the second-second clock signal, respectively, during a scan period in which a compensation gate signal is supplied to the display panel, and have different waveforms from the first-second clock signal and the second-second clock signal, respectively, during a blank period in which the compensation gate signal is not supplied to the display panel.

Abstract: Systems and methods are provided for a display device that includes a display unit. The display unit includes scan lines and pixels coupled to the scan lines. A timing controller operates in a first mode and a second mode and generates a start signal, based on a vertical synchronization signal provided from the outside. A scan driver generates a scan signal, based on the start signal, and sequentially provides the scan signal to the scan lines. The timing controller generates the start signal immediately after a pulse of the vertical synchronization signal is applied in the first mode, and generates the start signal before a pulse the vertical synchronization signal is applied in the second mode.

Abstract: A stage including a node control unit which controls a voltage of a first control node and a voltage of a second control node, in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, a node maintenance unit which maintains the voltage of the first control node to be constant in correspondence with the voltage of the second control node, and an output unit which supplies a first gate voltage supplied to a first power terminal or a second gate voltage supplied to a second power terminal to an output terminal in correspondence with the voltage of the first control node and the voltage of the second control node.

Abstract: A stage circuit includes a first substage circuit unit connected to first through third input terminals receiving a start signal, a first clock signal, and a second clock signal, respectively. The first substage circuit unit generates first and second operation signals based on the start signal and the first and second clock signals, and supplies a first scan signal to a first output terminal based on the first and second operation signals. The stage circuit further includes a second substage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal. The second substage circuit unit supplies a second scan signal to a second output terminal based on the first and second operation signals, the second clock signal, and the third clock signal. The first and second scan signals include a pulse of a low voltage level and a high voltage level, respectively.

Abstract: An organic light emitting diode (OLED) display includes: a display area comprising a plurality of pixel rows configured to emit light in response to a light emission signal; a light emission signal generator at the periphery of the display area, and including a plurality of light emission signal stages connected to the plurality of pixel rows; and a first high voltage transmission line and a second high voltage transmission line connected to the light emission signal generator, wherein the first high voltage transmission line is connected to a plurality of odd-numbered light emission signal stages among the plurality of light emission signal stages, and the second high voltage transmission line is connected to a plurality of even-numbered light emission signal stages among the plurality of light emission signal stages.

Abstract: An embodiment device for detecting a boundary of a road in a 3D point cloud using a cascade classifier includes a rule-based classifier configured to determine whether a received LiDAR cluster has a likelihood of becoming a candidate for the boundary of the road using a box parameter surrounding a point cloud constituting the LiDAR cluster and a point parameter, and a learning-based classifier configured to apply a machine-learning scheme to the LiDAR cluster selected as the candidate for the boundary of the road by the rule-based classifier to determine the LiDAR cluster to be the boundary of the road or an object other than the boundary of the road.

Abstract: A display device includes: pixels provided in a display area; data lines connected to the pixels, the data lines providing data signals to the pixels; scan lines connected to the pixels, the scan lines providing scan signals to the pixels; and dummy scan lines intersecting the data lines in a peripheral area surrounding the display area.

Abstract: A light-emitting display device includes first and second sub pixels each of which includes a driving transistor including first and second electrodes and a gate electrode, and being configured to control an electric current flowing from the first electrode to the second electrode according to a data voltage applied to a gate electrode, a light-emitting element connected to the second electrode, and a first capacitor disposed between a first sub supply voltage line to which a first supply voltage is applied and the second electrode. The first sub supply voltage line is disposed to overlap the second electrode. A capacitance of a first capacitor of the first sub pixel versus a capacitance of a first capacitor of the second sub pixel is selectively determined to correspond to an amount of the overlap between the first sub supply voltage line and the second electrode.

Abstract: An organic light emitting display device includes a pixel, a data line, a first scan line, a second scan line, and a scan driver. The pixel includes a first transistor, a second transistor, and a third transistor. A source of the first transistor is electrically connected to a drain of the third transistor. A source of the second transistor is configured to receive an initialization voltage. The data line is electrically connected to a source of the third transistor and may transmit a data voltage higher than the initialization voltage. The first scan line is electrically connected to a gate of the third transistor. The second scan line is electrically connected to a gate of the second transistor. The scan driver may provide an initializing scan signal to the second scan line at least two horizontal periods before providing an initial scan signal to the first scan line.

Abstract: Disclosed are a harmony symbol input device and method using a dedicated chord input unit. The harmony symbol input device includes: a musical notation provider configured to visualize and provide a musical notation; a chord input unit provider configured to provide a dedicated chord input unit for inputting a harmony symbol in each harmony section of the musical notation; and a harmony symbol display part configured to repeat an operation that provides highlighting for a specific harmony section in a progression order of the musical notation and displays the harmony symbol received from the dedicated chord input unit in relation to the highlighting.

Abstract: A display device includes: an organic light emitting diode (OLED); a pixel circuit configured to control an amount of a current flowing from a first power voltage to the OLED; and a gate line and a data line that are connected to the pixel circuit, the pixel circuit including: an auxiliary transistor including a gate electrode electrically connected to the data line and a first electrode and a second electrodes connected to the gate line, the first electrode and the second electrode of the auxiliary transistor being electrically connected to each other.

Abstract: A stage including a node control unit which controls a voltage of a first control node and a voltage of a second control node, in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, a node maintenance unit which maintains the voltage of the first control node to be constant in correspondence with the voltage of the second control node, and an output unit which supplies a first gate voltage supplied to a first power terminal or a second gate voltage supplied to a second power terminal to an output terminal in correspondence with the voltage of the first control node and the voltage of the second control node.

Abstract: A light-emitting display device includes first and second sub pixels each of which includes a driving transistor including first and second electrodes and a gate electrode, and being configured to control an electric current flowing from the first electrode to the second electrode according to a data voltage applied to a gate electrode, a light-emitting element connected to the second electrode, and a first capacitor disposed between a first sub supply voltage line to which a first supply voltage is applied and the second electrode. The first sub supply voltage line is disposed to overlap the second electrode. A capacitance of a first capacitor of the first sub pixel versus a capacitance of a first capacitor of the second sub pixel is selectively determined to correspond to an amount of the overlap between the first sub supply voltage line and the second electrode.

Abstract: A display device includes the following elements: a light emitting diode; a first transistor including a drain electrode, a source electrode, and a gate electrode, the drain electrode being connected to the light emitting diode; a second transistor connected between a data line and the source electrode; a third transistor connected between the drain electrode and the gate electrode; and a fourth transistor connected between a first initialization voltage source and the gate electrode. The third transistor is off for a first period, on for a second period immediately following the first period, and off for a third period immediately following the second period. The fourth transistor is off for a fourth period, on for a fifth period immediately following the fourth period, and off for a sixth period immediately following the fifth period. The second period overlaps the fifth period.

Abstract: Provided herein is a display device including a plurality of pixels, wherein each pixel of the plurality of pixels includes: a driving transistor including a first electrode, a second electrode, and a first gate electrode; a first emission transistor including a third electrode coupled to the first electrode of the driving transistor, a fourth electrode, and a second gate electrode; and a second emission transistor including a fifth electrode coupled to the second electrode of the driving transistor, a sixth electrode, and a third gate electrode, wherein both the second gate electrode and the third gate electrode are coupled to an emission line, and wherein the first emission transistor is turned-on but the second emission transistor is turned-off, based on an emission signal supplied from the emission line.

Abstract: Disclosed are a harmony symbol input device and method using a dedicated chord input unit. The harmony symbol input device includes: a musical notation provider configured to visualize and provide a musical notation; a chord input unit provider configured to provide a dedicated chord input unit for inputting a harmony symbol in each harmony section of the musical notation; and a harmony symbol display part configured to repeat an operation that provides highlighting for a specific harmony section in a progression order of the musical notation and displays the harmony symbol received from the dedicated chord input unit in relation to the highlighting.

Abstract: A stage including a node control unit which controls a voltage of a first control node and a voltage of a second control node, in correspondence with a first input signal supplied to a first input terminal, a second input signal supplied to a second input terminal, and a third input signal supplied to a third input terminal, a node maintenance unit which maintains the voltage of the first control node to be constant in correspondence with the voltage of the second control node, and an output unit which supplies a first gate voltage supplied to a first power terminal or a second gate voltage supplied to a second power terminal to an output terminal in correspondence with the voltage of the first control node and the voltage of the second control node.

Abstract: A stage circuit includes a first substage circuit unit connected to first through third input terminals receiving a start signal, a first clock signal, and a second clock signal, respectively. The first substage circuit unit generates first and second operation signals based on the start signal and the first and second clock signals, and supplies a first scan signal to a first output terminal based on the first and second operation signals. The stage circuit further includes a second substage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal. The second substage circuit unit supplies a second scan signal to a second output terminal based on the first and second operation signals, the second clock signal, and the third clock signal. The first and second scan signals include a pulse of a low voltage level and a high voltage level, respectively.

Abstract: A display device includes the following elements: a light emitting diode; a first transistor including a drain electrode, a source electrode, and a gate electrode, the drain electrode being connected to the light emitting diode; a second transistor connected between a data line and the source electrode; a third transistor connected between the drain electrode and the gate electrode; and a fourth transistor connected between a first initialization voltage source and the gate electrode. The third transistor is off for a first period, on for a second period immediately following the first period, and off for a third period immediately following the second period. The fourth transistor is off for a fourth period, on for a fifth period immediately following the fourth period, and off for a sixth period immediately following the fifth period. The second period overlaps the fifth period.