Patents by Inventor Jong-Won Sean Lee

Jong-Won Sean Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8404514
    Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase-change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventors: Jong-Won Sean Lee, DerChang Kau, Gianpaolo Spadini
  • Patent number: 8278641
    Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Jong-Won Sean Lee, DerChang Kau, Gianpaolo Spadini
  • Publication number: 20110147695
    Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Jong-Won Sean Lee, Derchang Kau, Gianpaolo Spadini