Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other. The microprocessor is configured to decode the first command, map the first address to a non-volatile memory device, execute the first command relative to the first address mapped to the non-volatile memory device, and determine a relation between the first address and the second address. The microprocessor is further configured to selectively execute the second command relative to the second address mapped to the non-volatile memory device concurrently with the first command based on the relation between the first address and the second address.

Abstract: A memory controller includes first and second interfaces, a microprocessor, a register and a plane control unit. The first interface is configured to receive a first command and plane logic information of a plurality of planes in a memory device from a host. The microprocessor is coupled to the first interface, and configured to decode the first command to provide a corresponding second command, and to map the plane logic information to be suited to a non-volatile memory device. The register is configured to queue the second command and the mapped plane logic information. The second interface is configured to provide the second command and the queued plane logic information to the memory device. The plane control unit is configured to control multiple planes corresponding to portions of the queued plane logic information to perform concurrently the second command in the non-volatile memory device.

Abstract: A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other. The microprocessor is configured to decode the first command, map the first address to a non-volatile memory device, execute the first command relative to the first address mapped to the non-volatile memory device, and determine a relation between the first address and the second address. The microprocessor is further configured to selectively execute the second command relative to the second address mapped to the non-volatile memory device concurrently with the first command based on the relation between the first address and the second address.

Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.

Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.