Patents by Inventor Jong-Woo Han

Jong-Woo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110176744
    Abstract: An apparatus and method for image interpolation using an anisotropic Gaussian filter, the image interpolation apparatus including: an edge information calculator calculating a first edge orientation that is an orientation of an edge of each of a plurality of pixels that constitute an input low resolution image, and first edge orientation energy that is a maximal strength of the edge corresponding to the first edge orientation; an image enlarging unit calculating a second edge orientation and second edge orientation energy of each of pixels to be interpolated, which are obtained by subtracting reference pixels corresponding to each of the pixels of the low resolution image among a plurality of pixels that constitute the high resolution image that is obtained by enlarging the low resolution image, based on the first edge orientation and the first edge orientation energy of the adjacent reference pixels; and a pixel value calculator calculating a value of each of the pixels to be interpolated, by using an interp
    Type: Application
    Filed: January 27, 2010
    Publication date: July 21, 2011
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sung-Jea Ko, Jong-Woo Han, Sung-Hyun Cheon, Tae-Shick Wang
  • Publication number: 20110048778
    Abstract: A circuit board includes a board part including a pattern portion on one surface thereof, the pattern portion being electrically connected to a semiconductor chip, and an under-fill layer disposed on the board part and exposing the pattern portion to the outside, the under-fill layer flowing to cover the pattern portion by heat generated in mounting the semiconductor chip.
    Type: Application
    Filed: December 16, 2009
    Publication date: March 3, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Woo Han, Soon Gvu Yim, Young Do Kweon
  • Publication number: 20100187002
    Abstract: Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution.
    Type: Application
    Filed: April 15, 2009
    Publication date: July 29, 2010
    Inventors: Seung Seoup Lee, Soon Gyu Yim, Jong Woo Han
  • Publication number: 20090244864
    Abstract: Disclosed are a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof. The capacitor-embedded printed circuit board can include a core board, an insulation resin layer, which is stacked on the core board, a first electrode and a first circuit pattern, which are buried in the insulation resin layer, a dielectric layer, which is stacked on a surface of the insulation resin layer, a first adhesive resin layer, which is stacked on the dielectric layer, and a second electrode and a second circuit pattern, which are formed on a surface of the first adhesive resin layer to correspond with the first electrode. With the present invention, the manufacturing process can be simplified and the reliability of products can be improved by reducing the variation of the capacitor (C).
    Type: Application
    Filed: February 4, 2009
    Publication date: October 1, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Woon-Chun Kim, Sung Yi, Hwa-Sun Park, Sang-Chul Lee, Jong-Woo Han, Young-Do Kweon
  • Publication number: 20040261713
    Abstract: A monitoring system for a plasma deposition facility includes a current comparator comparing a sense current with a reference current to generate an error signal and/or a voltage comparator comparing a sense voltage between a cathode electrode and a body of the vacuum chamber with a reference voltage to generate an error signal. A gate unit may be provided to logically combine error signals generated by the current comparator and the voltage comparator to generate a system error signal indicating the presence of contaminate gas within a vacuum chamber in the plasma deposition facility.
    Type: Application
    Filed: May 3, 2004
    Publication date: December 30, 2004
    Inventors: Jin-Bok Kim, Jong-Woo Han