Abstract: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

Abstract: A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact.

Abstract: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

Abstract: A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact.

Abstract: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

Abstract: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

Abstract: Provided are highly reliable, high density stacked semiconductor packages including a plurality of semiconductor chips and a method of manufacturing the highly reliable, high density semiconductor package. An embodiment of the stacked semiconductor package includes upper and lower semiconductor packages that are sequentially stacked. The upper and lower semiconductor packages include inner leads connected to semiconductor chips. The lower semiconductor package may further include a plurality of outer leads connected to the inner leads of the lower semiconductor package and that extend outside a encapsulant to be electrically connected to the inner leads of the upper semiconductor package.