Abstract: A display substrate includes a data line disposed on a base substrate, a first pixel electrode disposed at a first side of the data line, a second pixel electrode disposed at a second side of the data line and a storage electrode overlapping with the data line. The storage electrode overlaps with the first pixel electrode by a first overlapping width, and overlaps with the second pixel electrode by a second overlapping width larger than the first overlapping width.

Abstract: An array substrate includes a gate line, a data line, a plurality of common electrodes, a shield electrode, and a pixel electrode. The gate line is extended along a first direction, and the data line is extended along a second direction. The common electrodes are formed in a plurality of pixel areas. The common electrodes are spaced apart from each other. The shield electrode is formed below the data line and formed between the common electrodes formed in the pixel areas adjacent to each other. The pixel electrode is overlapped with the common electrodes. The pixel electrode has a plurality of openings formed thereon. Therefore, an electric field of a common electrode pattern may prevent coupling between a pixel electrode and a data line, so that a distance between the pixel electrode and the data line may be minimized, and thus an aperture ratio and light transmittance may be enhanced.

Abstract: According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.

Abstract: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

Abstract: A gate drive circuit in which multiple stages are connected together one after each other. An n-th stage includes a pull-up part, a carry part, a pull-down part, a switching part, a first maintaining part and a second maintaining part. The pull-up part outputs a high voltage of a first clock signal. The carry part outputs a high voltage of the first clock signal. The pull-down part pulls-down the n-th gate signal into a first low voltage. The switching part outputs a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal. The first maintaining part maintains the n-th gate signal at the first low voltage in response to the first signal. The second maintaining part maintains the n-th gate signal at the first low voltage in response to a second signal.

Abstract: A liquid crystal display device for improving picture quality includes a common electrode formed on a first substrate, gate lines and data lines formed on a second substrate bonded to the first substrate by a sealing member with liquid crystals disposed therebetween, thin film transistors connected to the gate lines and to the data lines, pixel electrodes formed in subpixel regions, each pixel electrode having a long side in a direction of the gate lines and having a short side in a direction of the data lines fanout lines for supplying driving signals from the driving chips to the data lines, first conductive spacers formed between the fanout lines connected to different driving chips, for supplying a common voltage to the common electrode, and second conductive spacers formed between the fanout lines connected to the same driving chip, for supplying the common voltage to the common electrode.

Abstract: A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal wirings. The first signal wiring is disposed adjacent to a first side of the driving section, where the first side receives the signals from the wiring section. The second signal wiring is disposed adjacent to a portion that is disposed at an outer side of the driving section and the first signal wiring. Therefore, a signal applied to the first signal wiring is prevented from being delayed by the second signal wiring. Furthermore, a distortion of signal applied to the gate driver and a maloperation of the gate driver are prevented.

Abstract: A display substrate includes a gate line extended in one direction of a base substrate, a first data line extended in a direction crossing the gate line, a transverse storage line extended in the extending direction of the gate line and crossing the first data line, a longitudinal storage line extended in the extending direction of the first data line and crossing the transverse storage line, a portion of an overlapping area between the longitudinal storage line and the transverse storage line is exposed in a contact part region having an opening partially exposing the transverse storage line. A contact electrode covers the contact part opening and makes electrical contact with each of the transverse storage line and the longitudinal storage line.

Abstract: Provided is a liquid crystal display including, on an insulation substrate having a polygonal display area and a peripheral area surrounding the display area a first signal line, a second signal line crossing the first signal line, a plurality of switching elements connected to the first signal line and the second signal line and disposed in the display area, a plurality of pixel electrodes each connected to the switching element and disposed in the display area, and a shielding conductor disposed in the peripheral area and extending along at least one side of the polygonal display area.

Abstract: A display substrate includes a data line disposed on a base substrate, a first pixel electrode disposed at a first side of the data line, a second pixel electrode disposed at a second side of the data line and a storage electrode overlapping with the data line. The storage electrode overlaps with the first pixel electrode by a first overlapping width, and overlaps with the second pixel electrode by a second overlapping width larger than the first overlapping width.

Abstract: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Abstract: A display substrate includes a data line disposed on a base substrate, a first pixel electrode disposed at a first side of the data line, a second pixel electrode disposed at a second side of the data line and a storage electrode overlapping with the data line. The storage electrode overlaps with the first pixel electrode by a first overlapping width, and overlaps with the second pixel electrode by a second overlapping width larger than the first overlapping width.

Abstract: A display apparatus includes a display panel, a light source, a polarizer, and a transparent reflective element. The display panel includes a color filter including a first portion and a second portion in a pixel area. The first portion has a first light transmittance. The second portion has a second light transmittance higher than the first light transmittance. The light source provides a light to the display panel. The polarizer is disposed between the light source and the display. The polarizer polarizes the light. The transparent reflective element is spaced apart from the display panel. The transparent reflective element reflects an image provided from the display panel.

Abstract: A liquid crystal display device and a method of repairing bad pixels thereof, in which the bad pixels can be efficiently and easily repaired, includes a first insulating substrate, a gate wiring and a storage wiring arranged substantially parallel to each other in a first direction on the first insulating substrate, a data wiring intersecting the gate and storage wirings in an insulated manner and arranged substantially in a second direction, and a pixel electrode formed on a pixel area defined by the gate and data wirings. The storage wiring includes a horizontal portion arranged substantially in the first direction and at least a part of which does not overlap the pixel electrode, and a vertical portion branching off substantially in the second direction from the horizontal portion and overlapping the data wiring.

Abstract: A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

Abstract: According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.

Abstract: According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other on an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.

Abstract: A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on the gate insulating layer. The transparent conductive layer is patterned to form a pixel electrode. An opening is formed at a circumference of the pixel electrode. The opening minimizes misalignment during the manufacturing process and prevents shorts between a data line and the pixel electrode.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.