Patents by Inventor Jong Yeon Kim

Jong Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240239783
    Abstract: The present invention relates to a crystal form VII of a compound represented by chemical formula 1, a method for preparing same, and a pharmaceutical composition comprising same. The crystal form VII of the compound represented by chemical formula 1, according to the present invention, can be characterized by an XRD pattern, a DSC profile, and/or a TGA profile.
    Type: Application
    Filed: May 6, 2022
    Publication date: July 18, 2024
    Applicant: LG CHEM, LTD.
    Inventors: Ho Yeon LEE, Jin Ok HAM, Sang Dae LEE, Ji Yoon KIM, Jong Won PARK, Sung Won KIM, Seul Ah CHUN
  • Patent number: 12039705
    Abstract: An apparatus for classifying fake images according to an embodiment of the present disclosure includes an artifact remover configured to receive an input image to generate an artifact-removed image from which artifacts are removed, an artifact image generator configured to generate an artifact image by using a difference between the input image and the artifact removal image, and a determiner configured to determine whether the artifact image is a real image or a fake image by receiving the artifact image.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 16, 2024
    Assignees: CHUNG ANG University Industry Academic Cooperation Foundation, SAMSUNG SDS CO., LTD.
    Inventors: Yong Hyun Jeong, Jong Won Choi, Do Yeon Kim, Young Min Ro
  • Patent number: 12037338
    Abstract: The present disclosure provides a compound of Chemical Formula (1) or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same: wherein X, Z, R1 and R2 are as defined in the specification. The compound of Chemical Formula (1) or pharmaceutically acceptable salt thereof acts as a positive allosteric modulator of metabotropic glutamate receptor subtype 5 (mGluR5), thereby being useful in the prevention or treatment of disorder mediated by glutamate dysfunction and mGluR5.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: July 16, 2024
    Assignee: SK BIOPHARMACEUTICALS CO., LTD.
    Inventors: Chun Eung Park, Young Koo Jang, Yong Je Shin, Ji Yeon Kim, Seung Mo Ham, Yong Gil Kim, Hye Kyung Min, Soo Bong Cha, Hyo Jun Jung, Ju Young Lee, Seung Nam Han, Jin Yong Chung, Eun Ju Choi, Chan Mi Joung, Jong Sil Park, Ji Won Lee, Nahm Ryune Cho, Eun Ju Ryu, Cheol Young Maeng
  • Patent number: 12040351
    Abstract: A light emitting diode (LED) stack for a display including a first LED stack including a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, an intermediate bonding layer disposed between the first LED stack and the second LED stack to bond the second LED stack to the first LED stack, an upper bonding layer disposed between the second LED stack and the third LED stack to couple the third LED stack to the second LED stack, and a first hydrophilic material layer disposed between the first LED stack and the upper bonding layer.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 16, 2024
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee, Chang Yeon Kim, Chung Hoon Lee
  • Publication number: 20240186291
    Abstract: A semiconductor die stack structure includes a base die, a plurality of semiconductor die stack units, and bumps. Each of the plurality of semiconductor die stack units includes a lower semiconductor die and an upper semiconductor die. Each of the lower semiconductor die and the upper semiconductor die includes a body and a front-side pad structure. The front-side pad structure includes a front-side pad seed layer and a front-side pad pattern. The front-side pad pattern includes a first front-side pad portion, a second front-side pad portion, and a third front-side pad portion. The first front-side pad portion and the second front-side pad portion forms a staircase. The first front-side pad portion and the third front-side pad form a reverse staircase. The first front-side pad portion, the second front-side pad portion, and the third front-side pad include a same metal.
    Type: Application
    Filed: July 3, 2023
    Publication date: June 6, 2024
    Applicant: SK hynix Inc.
    Inventors: Sung Kyu KIM, Jong Yeon KIM, Song NA, Sang Hyuk LIM, Jong Oh KWON, Jin Woo PARK
  • Publication number: 20240120292
    Abstract: A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.
    Type: Application
    Filed: March 20, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventors: Jin Woong KIM, Jong Yeon KIM
  • Publication number: 20240105656
    Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Jun LEE, Jong Yeon KIM, Jong Hoon KIM, Ju Heon YANG, Mi Seon LEE
  • Patent number: 10690709
    Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 23, 2020
    Assignee: SUNKWANG LIGHTNING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin Kim, Jong-Yeon Kim, Wan-Seong Kwon, Dong-Min Kim, Yong-Su Kim, Byeong-U Kim
  • Publication number: 20190219620
    Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.
    Type: Application
    Filed: June 7, 2017
    Publication date: July 18, 2019
    Applicant: SUNKWANG LIGHTING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin KIM, Jong-Yeon KIM, Wan-Seong KWON, Dong-Min KIM, Yong-Su KIM, Byeong-U KIM
  • Patent number: 9590418
    Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 7, 2017
    Assignee: SUNKWANG LIGHTNING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin Kim, Jong-Yeon Kim, Jin-Yeong Lee, Wan-Seong Kwon, Dong-Min Kim, Yong-Su Kim
  • Publication number: 20160372919
    Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.
    Type: Application
    Filed: March 10, 2015
    Publication date: December 22, 2016
    Inventors: Dong-Jin KIM, Jong-Yeon KIM, Jin-Yeong LEE, Wan-Seong KWON, Dong-Min KIM, Yong-Su KIM
  • Patent number: 9076881
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hyeok Im, Jong-Yeon Kim, Tae-Je Cho, Un-Byoung Kang
  • Patent number: 8921918
    Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Kyoung-Hoon Kim, Woonkyung Lee, Wonseok Cho, Hoosung Cho, Jintaek Park, Jong-Yeon Kim, Sung-Min Hwang
  • Patent number: 8816407
    Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-yeon Kim, Tae-hong Min, Yeong-kwon Ko, Tae-je Cho
  • Publication number: 20140147974
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hyeok IM, Jong-Yeon KIM, Tae-Je CHO, Un-Byoung KANG
  • Patent number: 8643179
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Hyeok Im, Jong-Yeon Kim, Tae-Je Cho, Un-Byoung Kang
  • Publication number: 20130267558
    Abstract: Provided is a pharmaceutical composition for the treatment and prevention of alcoholic liver diseases, including cilostazol as an active ingredient. Cilostazol inhibits expression levels of TNF-? and FAS (fatty acid synthase) gene in a concentration-dependent manner, and also significantly inhibits the activity of caspase-3. Accordingly, cilostazol shows superior effects for the treatment or prevention of alcoholic liver diseases, in particular, alcoholic hepatitis compared to pentoxifylline which is conventionally used as a therapeutic agent for the treatment for alcoholic hepatitis. Thus, cilostazol is suitable for use as a drug for the treatment or prevention of alcoholic hepatitis.
    Type: Application
    Filed: October 7, 2011
    Publication date: October 10, 2013
    Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION YEUNGNAM UNIVERSITY
    Inventors: Jong-Yeon Kim, Jong-Ryul Eun, Youn-Ju Lee
  • Patent number: 8522115
    Abstract: A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju hyung Kim, Chang Seok Kang, Young Woo Park, Jung Dal Choi, Jong-Yeon Kim
  • Publication number: 20120119359
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 17, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hyeok Im, Jong-Yeon Kim, Tae-Je Cho, Un-Byoung Kang
  • Publication number: 20120098050
    Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 26, 2012
    Inventors: Jae-Joo SHIM, Kyoung-Hoon KIM, Woonkyung LEE, Wonseok CHO, Hoosung CHO, Jintaek PARK, Jong-Yeon KIM, Sung-Min HWANG