Patents by Inventor Jong Yeon Kim

Jong Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128653
    Abstract: Disclosed is a meta-structure. The meta-structure includes a lower electrode, a lower insulating layer on the lower electrode, a lower metal oxide layer on the lower insulating layer, a metal layer on the lower metal oxide layer, an upper metal oxide layer on the metal layer, an upper insulating layer on the upper metal oxide layer, and antenna electrodes on the upper insulating layer.
    Type: Application
    Filed: June 28, 2023
    Publication date: April 18, 2024
    Inventors: Yong Hae KIM, Chi-Sun HWANG, Joo Yeon KIM, Jaehyun MOON, Jong-Heon YANG, Kyunghee CHOI, Ji Hun CHOI
  • Patent number: 11961750
    Abstract: A magnetic transfer apparatus includes: a magnetomotive force source providing magnetic flux, a first magnetic flux distribution circuit connected to one end of the magnetomotive force source, having a single input terminal and a plurality of output terminals, and distributing the magnetic flux, and a second magnetic flux distribution circuit connected to the other end of the magnetomotive force source, having a single output terminal and a plurality of input terminals, and collecting the distributed magnetic flux. The output terminals of the first magnetic flux distribution circuit are disposed to be adjacent to each other to form a pair with the input terminals of the second magnetic flux distribution circuit.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 16, 2024
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Tae-Yeon Seong, Da-Hoon Lee, Jong-Ho Kim
  • Publication number: 20240120292
    Abstract: A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.
    Type: Application
    Filed: March 20, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventors: Jin Woong KIM, Jong Yeon KIM
  • Publication number: 20240122037
    Abstract: A display device includes a substrate that includes a display area and a non-display area, a display element layer disposed on the display area of the substrate, an opposing substrate that faces the substrate and the display element layer, a sealing member disposed on the non-display area and that couples the substrate and the opposing substrate, and a filler disposed between the substrate and the opposing substrate. A thickness of the filler varies in the range of 60% to 400% of a thickness of the sealing member.
    Type: Application
    Filed: June 21, 2023
    Publication date: April 11, 2024
    Inventors: Jae Heung HA, Jong Woo KIM, So Young OH, Woo Suk JUNG, Hee Yeon PARK, Chang Yeong SONG, Jong Kwang YUN
  • Patent number: 11955262
    Abstract: An inductor includes a first magnetic body having a toroidal shape and having a ferrite; and a second magnetic body configured to be different from the first magnetic body and including a metal ribbon, wherein the second magnetic body includes an outer magnetic body disposed on an outer circumferential surface of the first magnetic body and an inner magnetic body disposed on an inner circumferential surface of the first magnetic body, and each of the outer magnetic body and inner magnetic body is wound in a plurality of layers in a circumferential direction of the first magnetic body.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 9, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Mi Jin Lee, Ji Yeon Song, Yu Seon Kim, Jong Wook Lim, Seok Bae, Sang Won Lee
  • Publication number: 20240105656
    Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Jun LEE, Jong Yeon KIM, Jong Hoon KIM, Ju Heon YANG, Mi Seon LEE
  • Publication number: 20240101272
    Abstract: The present disclosure relates to a system and method for detecting an aircraft energy anomaly using an artificial neural network learning model. A system for detecting an aircraft energy anomaly using an artificial neural network learning model according to the present disclosure includes an input interface device for receiving ADS-B (Automatic Dependent Surveillance-Broadcast) data, a memory storing a program which generates a specific energy feature for energy state analysis by extending the ADS-B data through a preprocessing, and a processor for executing the program, wherein the processor generates an energy distribution model by the use of the specific energy feature, and performs artificial neural network-based energy anomaly learning.
    Type: Application
    Filed: July 10, 2023
    Publication date: March 28, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Noh-Sam PARK, Ji Yeon KIM, Jong Hyun JANG
  • Patent number: 11935912
    Abstract: A display apparatus including a thin film transistor (TFT) substrate; a first LED sub-unit, a second LED sub-unit, and a third LED sub-unit; first, second, third, and fourth electrode pads disposed between the TFT substrate and the first LED sub-unit; and connectors connecting the first, second, and third LED sub-units to a respective one of the electrode pads, in which the first, second, and third sub-units are configured to be independently driven; light generated from the first LED sub-unit is emitted to the outside of the display apparatus by passing through the second and third LED sub-units; light generated from the second LED sub-unit is emitted to the outside of the display apparatus by passing through the third LED sub-unit; and at least one of the connectors includes a first portion electrically connecting a first surface of the first LED sub-unit to the second electrode pad.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 19, 2024
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee, Chang Yeon Kim, Chung Hoon Lee
  • Publication number: 20240088197
    Abstract: A light emitting chip including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a first bonding layer interposed between the first and second LED sub-units, a second bonding layer interposed between second and third LED sub-units, and a first connection electrode electrically connected to and overlapping at least one of the first, second, and third LED sub-units, the first connection electrode having first and second opposing side surfaces, the first side surface having a first length and the second side surface having a second length, in which the difference in length between the first side surface and the second side surface of the first connection electrode is greater than a thickness of at least one of the LED sub-units.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Jong Min JANG, Chang Yeon KIM, Myoung Hak YANG
  • Publication number: 20240084259
    Abstract: The present invention relates to stem cell-derived mature cardiomyocytes and a cardiovascular disease model using same and, more specifically, to differentiation into mature ventricular cardiomyocytes by culturing stem cells in a medium containing FGF4 and ascorbic acid, and use of the differentiated mature ventricular cardiomyocytes as a cardiovascular disease cell model. The mature ventricular cardiomyocytes, obtained by culturing stem cells in a medium containing FGF4 and ascorbic acid and inducing the differentiation thereof, and cardiovascular disease cell model using same according to the present invention are very useful for screening for cardiovascular disease therapeutic agents and evaluation of the toxicity of new drugs.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 14, 2024
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Do-Sun LIM, Seung Cheol CHOI, Hyung Joon JOO, Jong-Ho KIM, Chi-Yeon PARK, Yongdoo PARK
  • Patent number: 11929262
    Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-in Won, Jong-kak Jang, Dong-woo Kang, Do-yeon Kim
  • Patent number: 10690709
    Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 23, 2020
    Assignee: SUNKWANG LIGHTNING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin Kim, Jong-Yeon Kim, Wan-Seong Kwon, Dong-Min Kim, Yong-Su Kim, Byeong-U Kim
  • Publication number: 20190219620
    Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.
    Type: Application
    Filed: June 7, 2017
    Publication date: July 18, 2019
    Applicant: SUNKWANG LIGHTING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin KIM, Jong-Yeon KIM, Wan-Seong KWON, Dong-Min KIM, Yong-Su KIM, Byeong-U KIM
  • Patent number: 9590418
    Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 7, 2017
    Assignee: SUNKWANG LIGHTNING PROTECTION TECHNICAL INSTITUTE INC.
    Inventors: Dong-Jin Kim, Jong-Yeon Kim, Jin-Yeong Lee, Wan-Seong Kwon, Dong-Min Kim, Yong-Su Kim
  • Publication number: 20160372919
    Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.
    Type: Application
    Filed: March 10, 2015
    Publication date: December 22, 2016
    Inventors: Dong-Jin KIM, Jong-Yeon KIM, Jin-Yeong LEE, Wan-Seong KWON, Dong-Min KIM, Yong-Su KIM
  • Patent number: 9076881
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hyeok Im, Jong-Yeon Kim, Tae-Je Cho, Un-Byoung Kang
  • Patent number: 8921918
    Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Kyoung-Hoon Kim, Woonkyung Lee, Wonseok Cho, Hoosung Cho, Jintaek Park, Jong-Yeon Kim, Sung-Min Hwang
  • Patent number: 8816407
    Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-yeon Kim, Tae-hong Min, Yeong-kwon Ko, Tae-je Cho
  • Publication number: 20140147974
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hyeok IM, Jong-Yeon KIM, Tae-Je CHO, Un-Byoung KANG
  • Patent number: 8643179
    Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Hyeok Im, Jong-Yeon Kim, Tae-Je Cho, Un-Byoung Kang