Patents by Inventor Jong-Yuh CHANG
Jong-Yuh CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9377701Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.Type: GrantFiled: April 27, 2015Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Patent number: 9373551Abstract: An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity.Type: GrantFiled: November 26, 2013Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Shiun Lu, Chun-Lang Chen, Shih-Hao Yang, Jong-Yuh Chang
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Publication number: 20150370158Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
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Publication number: 20150316489Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates.Type: ApplicationFiled: June 23, 2015Publication date: November 5, 2015Inventors: Biow-Hiem Ong, CHIH-CHIANG TU, Chien-Hung Lai, JONG-YUH CHANG, Kuang-Yu Liu
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Patent number: 9122175Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.Type: GrantFiled: October 11, 2012Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
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Publication number: 20150227038Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Patent number: 9063097Abstract: A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates.Type: GrantFiled: February 11, 2011Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Biow-Hiem Ong, Chien-Hung Lai, Chih-Chiang Tu, Jong-Yuh Chang, Kuang-Yu Liu
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Patent number: 9057961Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.Type: GrantFiled: July 21, 2014Date of Patent: June 16, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
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Publication number: 20150154326Abstract: The present disclosure relates to a method of inspecting a photomask to decrease false defects, which uses a plurality of image rendering models with varying emphasis on different design aspects, and an associated apparatus. In some embodiments, the method is performed by forming an integrated circuit (IC) design comprising a graphical representation of an integrated circuit. A first image rendering simulation is performed on the IC design using an initial image rendering model to determine a plurality of initial mask defects. A second image rendering simulation is performed on the IC design using a modified image rendering model that emphasizes a design aspect to determine a plurality of modified mask defects. By comparing the plurality of initial mask defects with the plurality of modified mask defects, falsely identified mask defects can be detected and eliminated.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.Inventors: Meng-Lin Lu, Ching-Ting Yang, Chun-Jen Chen, Chien-Hung Lai, Jong-Yuh Chang
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Patent number: 9017903Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.Type: GrantFiled: July 22, 2013Date of Patent: April 28, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Patent number: 8999611Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.Type: GrantFiled: March 7, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Publication number: 20150024306Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Publication number: 20140335446Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.Type: ApplicationFiled: July 21, 2014Publication date: November 13, 2014Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
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Publication number: 20140273301Abstract: An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity.Type: ApplicationFiled: November 26, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Shiun LU, Chun-Lang CHEN, Shih-Hao YANG, Jong-Yuh CHANG
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Publication number: 20140255825Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
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Patent number: 8818072Abstract: The present disclosure provides a method of inspecting a photolithographic mask wherein a design database is received, and a feature of the design database is adjusted by a bias factor to produce a biased database. Image rendering is performed on the biased database to produce a biased image. A mask is also created using the design database, and the mask is imaged to produce a mask image. The biased image is compared to the mask image, and a new value for the bias factor may be determined based on the comparison.Type: GrantFiled: August 25, 2010Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Biow-Hiem Ong, Rick Lai, Chih-Chiang Tu, Chia-Shih Lin, Jong-Yuh Chang
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Patent number: 8792078Abstract: An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask.Type: GrantFiled: April 26, 2010Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ming Lin, Chien-Chao Huang, Jong-Yuh Chang, Chia-Wei Chang, Boming Hsu
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Patent number: 8785083Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.Type: GrantFiled: June 1, 2012Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
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Publication number: 20140106262Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.Type: ApplicationFiled: October 11, 2012Publication date: April 17, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
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Patent number: 8629407Abstract: A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects.Type: GrantFiled: April 13, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hung Lai, Biow-Hiem Ong, Chia-Shih Lin, Jong-Yuh Chang, Chih-Chiang Tu