Patents by Inventor Jong-Yul Park
Jong-Yul Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817826Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.Type: GrantFiled: August 11, 2022Date of Patent: November 14, 2023Assignee: Electronics and Telecommunications Research InstituteInventors: Woojin Chang, Dong Min Kang, Byoung-Gue Min, Jong Yul Park, Jongmin Lee, Yoo Jin Jang, Kyu Jun Cho, Hong Gu Ji
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Publication number: 20230142553Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.Type: ApplicationFiled: August 11, 2022Publication date: May 11, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: Woojin CHANG, Dong Min KANG, BYOUNG-GUE MIN, JONG YUL PARK, JONGMIN LEE, YOO JIN JANG, KYU JUN CHO, Hong Gu JI
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Patent number: 10684320Abstract: Provided is a method of evaluating a performance of a suspended channel plasma wave device (PWD) to evaluate a terahertz emission possibility of the suspended channel PWD based on physical properties of the suspended channel PWD. The method includes an x-axis setting operation of setting an electron drift velocity to be an x-axis; a y-axis setting operation of setting a plasma wave velocity to be a y-axis; and a device performance determining operation of determining an operation of a device by generating a design window based on a plasma wave generation condition of the suspended channel PWD and a relational expression between the plasma wave velocity and the electron drift velocity.Type: GrantFiled: December 31, 2015Date of Patent: June 16, 2020Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)Inventors: Kyung Rok Kim, Jong Yul Park, Sung-Ho Kim, Yu-Jung Jung
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Publication number: 20180080974Abstract: Provided is a method of evaluating a performance of a suspended channel plasma wave device (PWD) to evaluate a terahertz emission possibility of the suspended channel PWD based on physical properties of the suspended channel PWD. The method includes an x-axis setting operation of setting an electron drift velocity to be an x-axis; a y-axis setting operation of setting a plasma wave velocity to be a y-axis; and a device performance determining operation of determining an operation of a device by generating a design window based on a plasma wave generation condition of the suspended channel PWD and a relational expression between the plasma wave velocity and the electron drift velocity.Type: ApplicationFiled: December 31, 2015Publication date: March 22, 2018Inventors: Kyung Rok KIM, Jong Yul PARK, Sung-Ho KIM, Yu-Jung JUNG
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Patent number: 9869711Abstract: A method for evaluating the performance of a plasma transistor comprises: setting a plasma wave velocity, which is adjusted by a gate overdrive voltage, as a first axis; setting an electronic drift velocity, which is adjusted by a drain-to-source voltage, as a second axis; setting a channel length as a third axis; and checking whether the plasma wave transistor is operated as a terahertz emitter according to a change in the performance parameter value of the plasma wave transistor on the basis of a relational expression among the first axis, the second axis, and the third axis.Type: GrantFiled: May 7, 2014Date of Patent: January 16, 2018Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)Inventors: Kyung Rok Kim, Jong Yul Park, Sung-Ho Kim
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Patent number: 9780198Abstract: Aspects of the present invention relate to a method for manufacturing a high-performance and low-power field effect transistor (FET) element of which surface roughness scattering is minimized or removed, comprising: a first step of etching a strained silicon substrate into a pin structure; a second step of stacking undoped SiGe thereon; a third step of etching the undoped SiGe; a fourth step of etching after performing lithography; a fifth step of stacking doped SiGe thereon; a sixth step of etching the doped SiGe after performing lithography; and a step of forming a transistor element by sequentially stacking an oxide and a gate metal on the doped SiGe and there is an effect of enabling the implementation of a Fin HEMT capable of having all of good channel controllability and a high on-current, which are advantages of a FinFET, and high electron mobility, which is an advantage of an HEMT.Type: GrantFiled: December 9, 2014Date of Patent: October 3, 2017Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)Inventors: Kyung Rok Kim, Sung Ho Kim, Jong Yul Park
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Publication number: 20170243953Abstract: Aspects of the present invention relate to a method for manufacturing a high-performance and low-power field effect transistor (FET) element of which surface roughness scattering is minimized or removed, comprising: a first step of etching a strained silicon substrate into a pin structure; a second step of stacking undoped SiGe thereon; a third step of etching the undoped SiGe; a fourth step of etching after performing lithography; a fifth step of stacking doped SiGe thereon; a sixth step of etching the doped SiGe after performing lithography; and a step of forming a transistor element by sequentially stacking an oxide and a gate metal on the doped SiGe and there is an effect of enabling the implementation of a Fin HEMT capable of having all of good channel controllability and a high on-current, which are advantages of a FinFET, and high electron mobility, which is an advantage of an HEMT.Type: ApplicationFiled: December 9, 2014Publication date: August 24, 2017Applicant: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)Inventors: Kyung Rok Kim, Sung Ho Kim, Jong Yul Park
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Publication number: 20170010317Abstract: A method for evaluating the performance of a plasma transistor comprises: setting a plasma wave velocity, which is adjusted by a gate overdrive voltage, as a first axis; setting an electronic drift velocity, which is adjusted by a drain-to-source voltage, as a second axis; setting a channel length as a third axis; and checking whether the plasma wave transistor is operated as a terahertz emitter according to a change in the performance parameter value of the plasma wave transistor on the basis of a relational expression among the first axis, the second axis, and the third axis.Type: ApplicationFiled: May 7, 2014Publication date: January 12, 2017Inventors: Kyung Rok KIM, Jong Yul PARK, Sung-Ho KIM
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Patent number: 6510094Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signType: GrantFiled: August 28, 2001Date of Patent: January 21, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Chung, Chang-Rae Kim, Sang-Jib Han, Jong-Yul Park
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Patent number: 6473353Abstract: A refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation is provided. In the refresh method for a semiconductor memory device, when refresh operation is requested, the low address for the refresh operation is latched, and it is determined whether a normal operation command is inputted into the semiconductor memory device. If the normal operation command is inputted into the device, block selection bits of a low address for normal operation is compared with block selection bits of the latched low address for the refresh operation. When block selection bits of both low addresses are the same, a word line for the refresh operation is activated by decoding the latched low address for the refresh operation. A word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for refresh operation is decoded.Type: GrantFiled: November 14, 2001Date of Patent: October 29, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-kue Jo, Jong-yul Park
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Patent number: 6463002Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.Type: GrantFiled: March 8, 2001Date of Patent: October 8, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han
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Publication number: 20020141269Abstract: A refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation is provided. In the refresh method for a semiconductor memory device, when refresh operation is requested, the low address for the refresh operation is latched, and it is determined whether a normal operation command is inputted into the semiconductor memory device. If the normal operation command is inputted into the device, block selection bits of a low address for normal operation is compared with block selection bits of the latched low address for the refresh operation. When block selection bits of both low addresses are the same, a word line for the refresh operation is activated by decoding the latched low address for the refresh operation. A word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for refresh operation is decoded.Type: ApplicationFiled: November 14, 2001Publication date: October 3, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Seong-kue Jo, Jong-yul Park
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Publication number: 20020054530Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signType: ApplicationFiled: August 28, 2001Publication date: May 9, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Min-Chul Chung, Chang-Rae Kim, Sang-Jib Han, Jong-Yul Park
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Publication number: 20020001247Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation.Type: ApplicationFiled: March 8, 2001Publication date: January 3, 2002Applicant: Samsung ElectronicsInventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han
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Patent number: 6275437Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.Type: GrantFiled: June 30, 2000Date of Patent: August 14, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han