Abstract: Each memory block in the flash memory is added with corresponding information bit(s) that store(s) information indicating whether erasure of the memory block has been completed before power-off. This allows easily finding out which memory block in the flash memory is undergoing an erase operation at the time of power-off. When the flash memory is powered on again, the information in the corresponding information bit(s) of the memory blocks may be read out and checked to determine whether there is any memory block of which the erasure had not been completed before the last power-off. If so, the memory blocks in the flash memory will be reprogrammed during the re-powering. This can avoid possible failure in reading data from some memory cells in the flash memory.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; a pad disposed on the first insulating layer and having a top surface exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than the top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall includes: a first inner wall extending from the bottom surface and having a first inclination angle; and a second inner wall extending from the first inner wall and having a second inclination angle different from the first inclination angle.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a plurality of pads disposed on the first insulating layer and having top surfaces exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than a top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall is perpendicular to top or bottom surface of the second insulating layer, wherein the bottom surface of the cavity includes: a first bottom surface positioned lower than a top surface of the pad and positioned outside an arrangement region of the plurality of pads; and a second bottom surface positioned lower than the top surface of the pad and positioned inside the arrangement region of the plurality of pads, and wherein a height of the first bottom surface is different from a height of the second bottom surface.

Abstract: A flash memory, a method of erasing the flash memory and an electronic system are disclosed. Each memory block in the flash memory is added with corresponding information bit(s) that store(s) information indicating whether erasure of the memory block has been completed before power-off. This allows easily finding out which memory block in the flash memory is undergoing an erase operation at the time of power-off. When the flash memory is powered on again, the information in the corresponding information bit(s) of the memory blocks may be read out and checked to determine whether there is any memory block of which the erasure had not been completed before the last power-off. If so, the memory blocks in the flash memory will be reprogrammed during the re-powering. This can avoid possible failure in reading data from some memory cells in the flash memory.

Abstract: A memory system may include a memory device including a plurality of planes each including a plurality of memory blocks; and a controller suitable for storing first and second command data corresponding to first and second commands in a first and a second sub-buffer of a buffer or one or more extra page buffers among page buffers included in the plurality of planes, respectively, according to a priority information and a size information of the first and second commands, and performing first and second command operations in response to the first and second commands, respectively.

Abstract: A memory system includes a memory device including a plurality of memory blocks; and a controller suitable for performing read and write operations respectively in response to read and write commands, and update map data, which is stored in a buffer, as a result of the operations according to priority information of data stored in the memory blocks.

Abstract: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Abstract: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Abstract: Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in synchronization with a second clock and sensing and amplifying data of the other local bit-line. Accordingly, two precharged local bit-lines are not adjacent to each other, thereby eliminating a coupling noise effect. In addition, the time for performing the precharging operation and the sensing operation is easily secured, compared to the prior precharging method in which corresponding local bit-lines are precharged at every clock.

Abstract: Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in synchronization with a second clock and sensing and amplifying data of the other local bit-line. Accordingly, two precharged local bit-lines are not adjacent to each other, thereby eliminating a coupling noise effect. In addition, the time for performing the precharging operation and the sensing operation is easily secured, compared to the prior precharging method in which corresponding local bit-lines are precharged at every clock.

Abstract: Disclosed is a sense amplifier. The sense amplifier comprises a sensing unit for sensing data stored at a memory cell, a reference voltage generator having a reference cell, for generating a reference voltage, an equalizer that makes same the output of the sensing unit and the output of the reference voltage generator, before a word line of the memory cell is enabled, and is then disabled, and a comparator for comparing the output of the sensing unit and the output of the reference voltage generator. Therefore, the present invention can improve the sensing speed.

Abstract: A circuit for generating a trim bit signal in a flash memory device, comprises a control unit selected by a trim bit select signal and including a programmable and erasable cell, and an output unit for outputting a High level signal or a Low level signal through the trim bit signal output terminal depending on the program cell of the control unit.

Abstract: Disclosed is a block select circuit in a flash memory device. The block select circuit comprises a select unit including a flash memory cell that is programmable and erasable by a given voltage condition, for outputting a block select signal depending on address signals and a state of the flash memory cell, a high-voltage pumping unit for outputting a signal to keep a given high voltage according to the block select signal and the clock signal, and a switching unit for applying a given bias to a gate select line, a word line and a source select line of a flash memory cell block according to the output signal of the high-voltage pumping unit. A given voltage is not applied to a fail block by only the operation of programming the flash memory cell of an erase state. Therefore, it is possible to process a fail block even after being packaged.

Abstract: A NAND type flash memory device including a word line decoder is disclosed. The word line decoder includes a row decoder, a control unit and a driving unit. The row decoder receives an address of a given memory cell to produce a signal informing whether the memory cell is selected. The control unit outputs a positive or a negative voltage according as the memory cell was selected or not. The driving unit has NMOS transistors for outputting the negative voltage from sources to drains if the positive voltage outputted from the control unit is applied to gates of the NMOS transistors. The NMOS transistors prohibits the negative voltage inputted to the sources from being outputted to the drains if the negative voltage from the control unit is applied to the gates. The negative voltage inputted to the sources is applied to a P well of the NMOS transistors.

Abstract: Disclosed is a block select circuit in a flash memory device. The block select circuit comprises a select unit including a flash memory cell that is programmable and erasable by a given voltage condition, for outputting a block select signal depending on address signals and a state of the flash memory cell, a high-voltage pumping unit for outputting a signal to keep a given high voltage according to the block select signal and the clock signal, and a switching unit for applying a given bias to a gate select line, a word line and a source select line of a flash memory cell block according to the output signal of the high-voltage pumping unit. A given voltage is not applied to a fail block by only the operation of programming the flash memory cell of an erase state. Therefore, it is possible to process a fail block even after being packaged.

Abstract: Disclosed is a sense amplifier. The sense amplifier comprises a sensing unit for sensing data stored at a memory cell, a reference voltage generator having a reference cell, for generating a reference voltage, an equalizer that makes same the output of the sensing unit and the output of the reference voltage generator, before a word line of the memory cell is enabled, and is then disabled, and a comparator for comparing the output of the sensing unit and the output of the reference voltage generator. Therefore, the present invention can improve the sensing speed.

Abstract: Disclosed is a circuit for generating a trim bit signal in a flash memory device. The circuit comprises a control unit selected by a trim bit select signal and including a programmable and erasable cell, and an output unit for outputting a High level signal or a Low level signal through the trim bit signal output terminal depending on the program cell of the control unit. Thus, as important parameters could be controlled that decide the characteristics of the chip even after the package, the characteristics of the chip could be improved and the productivity could be thus improved.

Abstract: The present invention relates to a word line decoder in a NAND type flash memory device.

Abstract: The present invention relates to a level shifter. The level shifter comprise a first transistor turned on by a control signal, for transmitting Vcc to a first node; a second transistor turned on by the control signal, for transmitting a zero voltage level to the first node; a third transistor turned on by the Vcc, for transmitting the voltage level of the first node to a second node; a fourth transistor turned by the zero voltage level, for transmitting the voltage level of the first node to a third node; a fifth transistor turned on by the voltage level of the second node, for transmitting a first voltage level to an output; and a sixth transistor turned on by the voltage level of the third node, for transmitting a second voltage level to the output.

Abstract: The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.