Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A circuit board according to an embodiment includes a first insulating layer; and a second insulating layer disposed on an upper surface of the first insulating layer, wherein the second insulating layer includes a cavity, and the cavity has a planar shape including a plurality of convex parts convex toward an inner direction of the second insulating layer.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a first pattern layer disposed on an upper surface of the first insulating layer; and a second insulating layer disposed on the upper surface of the first insulating layer and an upper surface of the first pattern layer and including a cavity, wherein the upper surface of the first insulating layer includes a first upper surface corresponding to a lower surface of the cavity, and a second upper surface having a step difference from the first upper surface and not vertically overlapping the lower surface of the cavity, wherein the first pattern layer includes a first pattern part disposed on the first upper surface, and a second pattern part disposed on the second upper surface, and wherein a thickness of the first pattern part is smaller than a thickness of the second pattern part.

Abstract: Disclosed is a chemical-mechanical polishing slurry composition having a small change in pH over time under an acidic condition and thus being easy to store for a long time. The chemical-mechanical polishing slurry composition includes an abrasive; an amount of about 0.000006 to 0.01 weight % of an aluminum component based on the total weight of the polishing slurry composition; and water. The number of silanol groups on a surface of the abrasive and a content of the aluminum component satisfy the requirements of following Equation 1: 0.0005?(S*C)*100?4.5,??[Equation 1] wherein, S is the number of the silanol groups present on 1 nm2 of the abrasive surface (unit: number/nm2), and C is the content of the aluminum component (weight %) in the slurry composition.

Abstract: Disclosed is a chemical-mechanical polishing slurry composition having a small change in pH over time under an acidic condition and thus being easy to store for a long time. The chemical-mechanical polishing slurry composition includes an abrasive; an amount of about 0.000006 to 0.01 weight % of an aluminum component based on the total weight of the polishing slurry composition; and water. The number of silanol groups on a surface of the abrasive and a content of the aluminum component satisfy the requirements of following Equation 1: 0.0005?(S*C)*100?4.5,??[Equation 1] wherein, S is the number of the silanol groups present on 1 nm2 of the abrasive surface (unit: number/nm2), and C is the content of the aluminum component (weight %) in the slurry composition.

Abstract: Disclosed is a chemical-mechanical polishing slurry composition having a small change in pH over time under an acidic condition and thus being easy to store for a long time. The chemical-mechanical polishing slurry composition includes an abrasive; an amount of about 0.000006 to 0.01 weight % of an aluminum component based on the total weight of the polishing slurry composition; and water. The number of silanol groups on a surface of the abrasive and a content of the aluminum component satisfy the requirements of following Equation 1: 0.0005?(S*C)*100?4.5,??[Equation 1] wherein, S is the number of the silanol groups present on 1 nm2 of the abrasive surface (unit: number/nm2), and C is the content of the aluminum component (weight %) in the slurry composition.

Abstract: The present invention relates to a slurry composition for reducing scratches generated when polishing the metal film in a manufacturing process of a semiconductor integrated circuit, by lowering frictional force so that a temperature of the composition which may rise during the polishing is lowered, the thermal stability of the slurry is improved and the size increase of particles in the slurry is suppressed, and a method for reducing scratches using the same. The method comprises the steps of applying a slurry composition for polishing a metal film to a substrate on which the metal film is formed, the slurry composition containing an organic solvent including a nitrogen atom and a glycol-based organic solvent; and making a polishing pad to be contacted to the substrate and moving the polishing pad with respect to the substrate, thereby removing at least part of the metal film from the substrate.

Abstract: The present invention relates to a slurry composition for reducing scratches generated when polishing the metal film in a manufacturing process of a semiconductor integrated circuit, by lowering frictional force so that a temperature of the composition which may rise during the polishing is lowered, the thermal stability of the slurry is improved and the size increase of particles in the slurry is suppressed, and a method for reducing scratches using the same. The method comprises the steps of applying a slurry composition for polishing a metal film to a substrate on which the metal film is formed, the slurry composition containing an organic solvent including a nitrogen atom and a glycol-based organic solvent; and making a polishing pad to be contacted to the substrate and moving the polishing pad with respect to the substrate, thereby removing at least part of the metal film from the substrate.

Abstract: A display apparatus and a method thereof. The display apparatus includes a display with variable transparency, a sensor which senses a location of at least one of a person and an object, and a controller which determines proximity of the at least one of the person and the object to the display based on a result of the sensing by the sensor, and adjusts the transparency of the display differently according to a result of the determining. Accordingly, a user can easily recognize contents displayed on the display screen having high transparency in the display apparatus.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: A display apparatus and a method thereof. The display apparatus includes a display with variable transparency, a sensor which senses a location of at least one of a person and an object, and a controller which determines proximity of the at least one of the person and the object to the display based on a result of the sensing by the sensor, and adjusts the transparency of the display differently according to a result of the determining. Accordingly, a user can easily recognize contents displayed on the display screen having high transparency in the display apparatus.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

Abstract: Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which controls a second DRAM. Accordingly, a garbage cycle, i.e., an operation which wastes data transfer bandwidth, that may generate when a related art DRAM accessing apparatus is used, is removed.

Abstract: A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A MoSi2—Si3N4 composite coating which is coated on a surface of base materials. The MoSi2—Si3N4 composite coating on the surface of the base material can be formed by forming a Mo2N diffusion layer by vapor-depositing of nitrogen on the surface of the base material and forming a MoSi2—Si3N4 composite coating by vapor-depositing of silicon on the surface of the Mo2N diffusion layer, or the MoSi2—Si3N4 composite coating on the surface of the base material can be formed by forming a MoSi2 diffusion layer by vapor-depositing of silicon on a surface of a base material by the CVD method, transforming the MoSi2 diffusion layer into a Mo5Si3 diffusion layer by heating under a high-purity hydrogen or argon atmosphere, forming a MoSi2—Si3N4 composite diffusion layer by vapor-depositing of nitrogen on the surface of the MosSi3 diffusion layer by the CVD method and forming a MoSi2—Si3N4 composite coating by vapor-depositing of silicon on the surface of the MoSi2—Si3N4 composite diffusion layer.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.