Abstract: Surface-modified abrasive particles improving the polishing performance of an insulating film and a metal film and having high-temperature stability are provided. An abrasive slurry composition comprising the same is also provided. Such abrasive particles are achieved by adjusting the ratio of the content of the modifier/the content of silica, the ratio of the carbon content in the modifier/the content of silica in the slurry after centrifugation, or the isoelectric point (IEP) difference of the modified abrasive particles in the slurry before and after centrifugation to a specific range during the surface modification of the abrasive particles.

Abstract: A display apparatus and a method thereof. The display apparatus includes a display with variable transparency, a sensor which senses a location of at least one of a person and an object, and a controller which determines proximity of the at least one of the person and the object to the display based on a result of the sensing by the sensor, and adjusts the transparency of the display differently according to a result of the determining. Accordingly, a user can easily recognize contents displayed on the display screen having high transparency in the display apparatus.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: A display apparatus and a method thereof. The display apparatus includes a display with variable transparency, a sensor which senses a location of at least one of a person and an object, and a controller which determines proximity of the at least one of the person and the object to the display based on a result of the sensing by the sensor, and adjusts the transparency of the display differently according to a result of the determining. Accordingly, a user can easily recognize contents displayed on the display screen having high transparency in the display apparatus.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

Abstract: Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which controls a second DRAM. Accordingly, a garbage cycle, i.e., an operation which wastes data transfer bandwidth, that may generate when a related art DRAM accessing apparatus is used, is removed.

Abstract: A keypad assembly mounted in a portable terminal is disclosed. The keypad assembly has a window keypad including a display window disposed on a front face of the portable terminal. A keypad top is integrally molded with the display window and simultaneously assembled on the front face of the portable terminal, thereby providing an easier assembly than known heretofore, as two parts can be assembled at the same time and additionally provide an elegant exterior front face.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

Abstract: A conductive coating composition and a method for producing coating layer using the same are disclosed. The conductive coating composition is capable of forming an antistatic coating layer on the protective film surface of display device. The conductive coating composition includes: 1 to 30 wt % of polyethylene dioxythiophene aqueous-dispersed solution; 5 to 15 wt % of water-soluble binder resin; 0.2 to 10 wt % of melamine resin; 6 to 40 wt % of alcohol solvent; 5 to 30 wt % of organic solvent selected from the group consisting of dimethyl sulfoxide, propyleneglycol methylether, N-methylpyrrolidone, ethyl-3-ethoxypropionate, propyleneglycol monomethyletheracetate, butylcarbitol and the mixtures thereof; and 10 to 50 wt % of water. The method for producing the conductive coating layer includes the steps of coating the conductive coating composition on a substrate; and drying the coating composition.

Abstract: Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which controls a second DRAM. Accordingly, a garbage cycle, i.e., an operation which wastes data transfer bandwidth, that may generate when a related art DRAM accessing apparatus is used, is removed.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: A conductive coating composition and a method for producing coating layer using the same are disclosed. The conductive coating composition is capable of forming an antistatic coating layer on the protective film surface of display device. The conductive coating composition includes: 1 to 30 wt % of polyethylene dioxythiophene aqueous-dispersed solution; 5 to 15 wt % of water-soluble binder resin; 0.2 to 10 wt % of melamine resin; 6 to 40 wt % of alcohol solvent; 5 to 30 wt % of organic solvent selected from the group consisting of dimethyl sulfoxide, propyleneglycol methylether, N-methylpyrrolidone, ethyl-3-ethoxypropionate, propyleneglycol monomethyletheracetate, butylcarbitol and the mixtures thereof; and 10 to 50 wt % of water. The method for producing the conductive coating layer includes the steps of coating the conductive coating composition on a substrate; and drying the coating composition.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: An apparatus and method for controlling a plurality of speakers, comprising an amplifier for amplifying and outputting a play signal to be played over the speakers; and at least one sensor disposed proximal to at least one of the speakers for sensing at least one environmental condition and outputting sensing data to a controller, wherein the controller adjusts the play signal to compensate for environmental changes based on the sensing data.