Abstract: A display device according to an embodiment comprises a substrate, a semiconductor layer disposed on the substrate, a first insulating layer, a first organic layer, a second insulating layer, and a second organic layer sequentially disposed on the semiconductor layer, a first electrode disposed on the second organic layer, a partition wall disposed on the first electrode and including a pixel opening, and a light emitting layer disposed in the pixel opening, wherein the second insulating layer includes a plurality of first openings, the plurality of first openings are filled with the second organic layer, and the thickness of the first organic layer and the second organic layer is about 1.5 ?m to about 3 ?m.

Abstract: A display device includes: a substrate; a conductive pattern layer disposed on the substrate; a buffer layer disposed on the conductive pattern layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a gate electrode disposed on the oxide pattern layer; and a connecting member electrically connected to the conductive pattern layer and the conductive region. The connecting member and the oxide pattern layer include a same material.

Abstract: A gate driving circuit includes: a first pull-up control circuit, a pull-up circuit, a pull-down circuit and an inverting circuit. The first pull-up control circuit applies a previous carry signal which is one of carry signals of previous stages to a first control node in response to the previous carry signal. The pull-up circuit outputs a gate clock signal as a gate output signal in response to a signal of the first control node. The pull-down circuit outputs a second low voltage as the gate output signal in response to a first next carry signal which is one of carry signals of next stages. The inverting circuit outputs one of a first signal and a first low voltage to a third control node in response to the first signal and a signal of a second control node.

Abstract: A method of evaluating a display driving element includes controlling a transistor to be turned off, where the transistor is connected to a first end of a target driving transistor of a test element group (TEG) disposed in a non-display area of a display panel, and measuring characteristics of the target driving transistor through pads connected to respective terminals of the target driving transistor.

Abstract: A display device includes a pixel. The pixel includes a light-emitting element, a first transistor which controls a driving current flowing through the light-emitting element, and including a gate connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second transistor which transmits a data voltage to a fourth node in response to a first gate signal, a storage capacitor connected between the first node and the fourth node, and an emission control transistor which transmits a first power voltage to the second node in response to a second gate signal or a first emission signal, including a first gate which receives the first emission signal and a second gate which receives the second gate signal, and being an oxide n-channel metal oxide semiconductor (NMOS) transistor.

Abstract: A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

Abstract: A test circuit includes: a metal pattern disposed in a first area; a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages, each of which outputs a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and which receives the test gate signal.

Abstract: A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

Abstract: A gate driving circuit includes: a first pull-up control circuit, a pull-up circuit, a pull-down circuit and an inverting circuit. The first pull-up control circuit applies a previous carry signal which is one of carry signals of previous stages to a first control node in response to the previous carry signal. The pull-up circuit outputs a gate clock signal as a gate output signal in response to a signal of the first control node. The pull-down circuit outputs a second low voltage as the gate output signal in response to a first next carry signal which is one of carry signals of next stages. The inverting circuit outputs one of a first signal and a first low voltage to a third control node in response to the first signal and a signal of a second control node.

Abstract: A display device includes: a substrate; a conductive pattern layer disposed on the substrate; a buffer layer disposed on the conductive pattern layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a gate electrode disposed on the oxide pattern layer; and a connecting member electrically connected to the conductive pattern layer and the conductive region. The connecting member and the oxide pattern layer include a same material.

Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

Abstract: A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.