Patents by Inventor Jonggab KIL

Jonggab KIL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for reducing switching jitter
    Patent number: 10181940
    Abstract: Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Jonggab Kil
  • APPARATUSES AND METHODS FOR REDUCING SWITCHING JITTER
    Publication number: 20170005781
    Abstract: Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventor: Jonggab Kil
  • Apparatuses and methods for reducing switching jitter
    Patent number: 9473291
    Abstract: Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventor: Jonggab Kil
  • SYMMETRICALLY COUPLED DIFFERENTIAL CHANNEL
    Publication number: 20160179739
    Abstract: A stream of binary data is converted into a stream of symbols according to a three-phase encoding scheme and send the symbols on a physical link. The link includes one or more lanes, each lane including a set of three conductors. The set of three conductors are to be oriented so that each conductor in the set is equidistant from the other two conductors in the set.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Jonggab Kil, Ravindra Rudraraju, Edward W. Gong
  • Skew tolerant clock recovery architecture
    Patent number: 9246666
    Abstract: Described is an apparatus which comprises: a comparator unit to receive at least three data signals with respective clock signals embedded in the at least three data signals, the comparator unit to provide first, second, and third clock signals; and a delay unit coupled to the comparator unit, the delay unit to receive the first, second and third clock signals to generate delayed versions of the first, second and third clock signals respectively.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventor: Jonggab Kil
  • APPARATUSES AND METHODS FOR REDUCING SWITCHING JITTER
    Publication number: 20160013926
    Abstract: Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventor: Jonggab Kil
  • SKEW TOLERANT CLOCK RECOVERY ARCHITECTURE
    Publication number: 20150280896
    Abstract: Described is an apparatus which comprises: a comparator unit to receive at least three data signals with respective clock signals embedded in the at least three data signals, the comparator unit to provide first, second, and third clock signals; and a delay unit coupled to the comparator unit, the delay unit to receive the first, second and third clock signals to generate delayed versions of the first, second and third clock signals respectively.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventor: Jonggab KIL