Patents by Inventor Jong Han Lee
Jong Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240321876Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.Type: ApplicationFiled: June 7, 2024Publication date: September 26, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Seong-Ho SONG, Jong Han LEE, Jong Ha PARK, Jae Hyun LEE, Jong Hoon BAEK, Da Bok JEONG
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Patent number: 12040324Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.Type: GrantFiled: August 18, 2021Date of Patent: July 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Song, Jong Han Lee, Jong Ha Park, Jae Hyun Lee, Jong Hoon Baek, Da Bok Jeong
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Publication number: 20230187446Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: ApplicationFiled: December 16, 2022Publication date: June 15, 2023Inventors: Min-Seok JO, Jae-Hyun LEE, Jong-Han LEE, Hong-Bae PARK, Dong-Soo LEE
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Patent number: 11532624Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: GrantFiled: December 12, 2018Date of Patent: December 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Seok Jo, Jae-Hyun Lee, Jong-Han Lee, Hong-Bae Park, Dong-Soo Lee
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Patent number: 11388859Abstract: The present invention relates to an auxiliary wheel for a lawn mower which includes an installation unit coupled to a main body of a lawn mower, a swing unit coupled to the installation unit to be swingable in one direction or the other direction, a wheel unit connected to the swing unit to be swingable with the swing unit, and a fixing unit installed on an outer portion of the installation unit and configured to fix the swing unit to be swingable in the other direction. When the wheel unit swings in the one direction, the main body is pressed against the ground, and when the wheel unit swings in the other direction, the main body is spaced apart from the ground.Type: GrantFiled: January 2, 2020Date of Patent: July 19, 2022Assignee: LS MTRON LTD.Inventors: Jung Sik Ki, Jae Seop Park, Gi Myeong Park, Dong Joo Kim, Jong Han Lee
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Publication number: 20220059530Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.Type: ApplicationFiled: August 18, 2021Publication date: February 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Seong-Ho SONG, Jong Han LEE, Jong Ha PARK, Jae Hyun LEE, Jong Hoon BAEK, Da Bok JEONG
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Publication number: 20200214211Abstract: The present invention relates to an auxiliary wheel for a lawn mower which includes an installation unit coupled to a main body of a lawn mower, a swing unit coupled to the installation unit to be swingable in one direction or the other direction, a wheel unit connected to the swing unit to be swingable with the swing unit, and a fixing unit installed on an outer portion of the installation unit and configured to fix the swing unit to be swingable in the other direction. When the wheel unit swings in the one direction, the main body is pressed against the ground, and when the wheel unit swings in the other direction, the main body is spaced apart from the ground.Type: ApplicationFiled: January 2, 2020Publication date: July 9, 2020Inventors: Jung Sik KI, Jae Seop PARK, Gi Myeong PARK, Dong Joo KIM, Jong Han LEE
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Patent number: 10636886Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of theType: GrantFiled: November 1, 2018Date of Patent: April 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min Seok Jo, Jae Hyun Lee, Jong Han Lee, Hong Bae Park
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Patent number: 10566433Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.Type: GrantFiled: July 9, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Hyuk Yim, Wan-Don Kim, Jong-Han Lee, Hyung-Suk Jung, Sang-Jin Hyun
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Patent number: 10529817Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.Type: GrantFiled: July 23, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yeol Song, Wan-don Kim, Su-young Bae, Dong-soo Lee, Jong-han Lee, Hyung-suk Jung, Sang-jin Hyun
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Publication number: 20190363084Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: ApplicationFiled: December 12, 2018Publication date: November 28, 2019Inventors: Min-Seok JO, Jae-Hyun LEE, Jong-Han LEE, Hong-Bae PARK, Dong-Soo LEE
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Publication number: 20190305099Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of theType: ApplicationFiled: November 1, 2018Publication date: October 3, 2019Inventors: Min Seok JO, Jae Hyun LEE, Jong Han LEE, Hong Bae PARK
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Publication number: 20190189767Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.Type: ApplicationFiled: July 23, 2018Publication date: June 20, 2019Applicant: Sumsung Electronics Co., Ltd.Inventors: Jae-yeol SONG, Wan-don Kim, Su-young Bae, Dong-soo Lee, Jong-han Lee, Hyung-suk Jung, Sang-jin Hyun
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Publication number: 20190157410Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.Type: ApplicationFiled: July 9, 2018Publication date: May 23, 2019Inventors: Jeong-Hyuk Yim, Wan-Don KIM, Jong-Han LEE, Hyung-Suk JUNG, Sang-Jin HYUN
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Patent number: 9728463Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.Type: GrantFiled: July 13, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-jin Lim, Gi-gwan Park, Sang-yub Ie, Jong-han Lee, Jeong-hyuk Yim, Hye-ri Hong
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Publication number: 20170062211Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.Type: ApplicationFiled: July 13, 2016Publication date: March 2, 2017Inventors: Ha-jin LIM, Gi-gwan PARK, Sang-yub IE, Jong-han LEE, Jeong-hyuk YIM, Hye-ri HONG
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Patent number: 9470447Abstract: An ice maker and a water purifier capable of making ice using two water trays. The water purifier having an ice maker includes a water tray member comprising an ice-making water tray holding ice-making raw water to make ice using an ice-making unit, and an auxiliary water tray holding ice-making raw water remaining in the ice-making water tray in the course of cooling the ice-making raw water by means of the ice-making unit and removing the ice-making raw water from the ice-making water tray; an ice reservoir storing ice made in the ice-making unit; a cold water storage tank cooling water held therein using the ice made in the ice-making unit; and a guide member guiding the ice made in the ice-making unit so that the ice is selectively fed to either the ice reservoir or the cold water storage tank.Type: GrantFiled: January 30, 2015Date of Patent: October 18, 2016Assignee: WOONGJIN COWAY CO. LTD.Inventors: Jong-Han Lee, Jung-Chul Park, Hee-Do Jung, Hyun-Woo Lee
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Publication number: 20150128634Abstract: An ice maker and a water purifier capable of making ice using two water trays. The water purifier having an ice maker includes a water tray member comprising an ice-making water tray holding ice-making raw water to make ice using an ice-making unit, and an auxiliary water tray holding ice-making raw water remaining in the ice-making water tray in the course of cooling the ice-making raw water by means of the ice-making unit and removing the ice-making raw water from the ice-making water tray; an ice reservoir storing ice made in the ice-making unit; a cold water storage tank cooling water held therein using the ice made in the ice-making unit; and a guide member guiding the ice made in the ice-making unit so that the ice is selectively fed to either the ice reservoir or the cold water storage tank.Type: ApplicationFiled: January 30, 2015Publication date: May 14, 2015Applicant: WOONGJIN COWAY CO. LTD.Inventors: Jong-Han LEE, Jung-Chul PARK, Hee-Do JUNG, Hyun-Woo LEE
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Patent number: 8355468Abstract: A carrier frequency estimation method and apparatus is provided for improving frequency estimation performance in an Orthogonal Frequency Division Multiplexing (OFDM) communication system. The frequency estimation method for a wireless communication system includes summing correlations of four pairs of reference symbols transmitted at different frequency-time resource blocks in a pattern, each pair including two closest reference symbols; calculating a statistical value (E) by accumulating the summed correlation in a frequency direction; and estimating a frequency offset using an angle extracted from the statistical value (E).Type: GrantFiled: November 27, 2009Date of Patent: January 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Jin Ro, Jong Han Lee
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Publication number: 20110036115Abstract: There is provided an ice maker and a water purifier having the same capable of effectively making ice using two water trays. The water purifier having an ice maker includes a water tray member comprising an ice-making water tray holding ice-making raw water to make ice using an ice-making unit, and an auxiliary water tray holding ice-making raw water remaining in the ice-making water tray in the course of cooling the ice-making raw water by means of the ice-making unit and removing the ice-making raw water from the ice-making water tray; an ice reservoir storing ice made in the ice-making unit; a cold water storage tank cooling water held therein using the ice made in the ice-making unit; and a guide member guiding the ice made in the ice-making unit so that the ice is selectively fed to either the ice reservoir or the cold water storage tank.Type: ApplicationFiled: March 31, 2009Publication date: February 17, 2011Applicant: Woongjin Coway Co., Ltd.Inventors: Jong-Han Lee, Jung-Chul Park, Hyun-Woo Lee, Hee-Do Jung