Abstract: A method of manufacturing a composite anode for a lithium ion battery and a composite anode for a lithium ion battery manufactured thereby. According to the method provide herein, since a metal catalyst precursor is reduced using Joule heating to obtain a carbon-metal catalyst composite layer, composite anode for a lithium ion battery having a large area in a short period of time can be provided, which is excellent in terms of economic feasibility. Further, since it is possible to manufacture a composite anode for a lithium ion battery with the improved lithium electrodeposition density and reversibility of lithium ions, a composite anode for a lithium ion battery having high capacity and improved life stability can be obtained.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.

Abstract: Provided are a triple redundant digital protective relay and an operating method therefor. The triple redundant digital protective relay according to the present invention includes: three power monitoring control devices which have a triple redundant structure and control a circuit breaker for separating a failed power system based on a 2 out of 3 voting using real-time mutual data communication; and a central communication device which acquires data related to an operating state of the power system from the three power monitoring control devices and manages the acquired data related to the operating state of the power system.

Abstract: An electronic device includes a transistor. The transistor includes: a substrate including an active region that extends in a first direction; a gate structure disposed in the substrate and crossing the active region in a second direction that crosses the first direction; recesses disposed in the active region on two sides of the gate structure in the first direction, a center of a bottom surface of a first recess being more depressed in a third direction than two edges of the bottom surface along the first direction, the third direction being perpendicular to the first and second directions; an insulating layer disposed in the first recess; and a junction layer disposed over the insulating layer in the first recess in the third direction, a top surface of the insulating layer being below the two edges of the bottom surface and having a smaller curvature than the bottom surface.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.

Abstract: Provided are a triple redundant digital protective relay and an operating method therefor. The triple redundant digital protective relay according to the present invention includes: three power monitoring control devices which have a triple redundant structure and control a circuit breaker for separating a failed power system based on a 2 out of 3 voting using real-time mutual data communication; and a central communication device which acquires data related to an operating state of the power system from the three power monitoring control devices and manages the acquired data related to the operating state of the power system.

Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.

Abstract: Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.

Abstract: Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.

Abstract: Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.