Patents by Inventor Jonghoon Baek

Jonghoon Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12563784
    Abstract: The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: February 24, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyun Lee, Jonghan Lee, Jonghoon Baek, Taegon Kim, Yujin Jung
  • Patent number: 12531206
    Abstract: The present disclosure relates to a method and apparatus for controlling a plasma sheath near a substrate edge. Changing the voltage/current distribution across the inner electrode and the outer electrode with in the substrate assembly facilitates the spatial distribution of the plasma across the substrate. The method includes providing a first radio frequency power to a central electrode embedded in a substrate support assembly, providing a second radio frequency power to an annular electrode embedded in the substrate support assembly at a location different than the central electrode, wherein the annular electrode circumferentially surrounds the central electrode, monitoring parameters of the first and second radio frequency power, and adjusting one or both of the first and second radio frequency power based on the monitored parameters.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: January 20, 2026
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Edward P. Hammond, IV, Jonghoon Baek
  • Publication number: 20260006845
    Abstract: A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.
    Type: Application
    Filed: September 3, 2025
    Publication date: January 1, 2026
    Inventors: Jaehyun Lee, Jonghan Lee, Hyungkoo Kang, Jonghoon Baek
  • Patent number: 12432972
    Abstract: A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: September 30, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun Lee, Jonghan Lee, Hyungkoo Kang, Jonghoon Baek
  • Publication number: 20250085643
    Abstract: In some general aspects, a surface of a structure within a chamber of an extreme ultraviolet (EUV) light source is cleaned using a method. The method includes generating a plasma state of a material that is present at a location adjacent to a non-electrically conductive body that is within the chamber. The generation of the plasma state of the material includes electromagnetically inducing an electric current at the location adjacent the non-electrically conductive body to thereby transform the material that is adjacent the non-electrically conductive body from a first state into the plasma state. The plasma state of the material includes plasma particles, at least some of which are free radicals of the material. The method also includes enabling the plasma particles to pass over the structure surface to remove debris from the structure surface without removing the structure from the chamber of the EUV light source.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 13, 2025
    Inventors: Chunguang Xia, Jonghoon Baek, John Tom Stewart, IV, Andrew David LaForge, Deniz Van Heijnsbergen, David Robert Evans, Nina Vladimirovna Dziomkina, Yue Ma
  • Patent number: 12189313
    Abstract: In some general aspects, a surface of a structure within a chamber of an extreme ultraviolet (EUV) light source is cleaned using a method. The method includes generating a plasma state of a material that is present at a location adjacent to a non-electrically conductive body that is within the chamber. The generation of the plasma state of the material includes electromagnetically inducing an electric current at the location adjacent the non-electrically conductive body to thereby transform the material that is adjacent the non-electrically conductive body from a first state into the plasma state. The plasma state of the material includes plasma particles, at least some of which are free radicals of the material. The method also includes enabling the plasma particles to pass over the structure surface to remove debris from the structure surface without removing the structure from the chamber of the EUV light source.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 7, 2025
    Assignee: ASML Netherlands B.V.
    Inventors: Chunguang Xia, Jonghoon Baek, John Tom Stewart, IV, Andrew David LaForge, Deniz Van Heijnsbergen, David Robert Evans, Nina Vladimirovna Dziomkina, Yue Ma
  • Patent number: 12136536
    Abstract: The present disclosure relates to a method and apparatus for controlling a plasma sheath near a substrate edge. Changing the voltage/current distribution across the inner electrode and the outer electrode with in the substrate assembly facilitates the spatial distribution of the plasma across the substrate. The method includes providing a first radio frequency power to a central electrode embedded in a substrate support assembly, providing a second radio frequency power to an annular electrode embedded in the substrate support assembly at a location different than the central electrode, wherein the annular electrode circumferentially surrounds the central electrode, monitoring parameters of the first and second radio frequency power, and adjusting one or both of the first and second radio frequency power based on the monitored parameters.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 5, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Edward P. Hammond, IV, Jonghoon Baek
  • Publication number: 20240222081
    Abstract: The present disclosure relates to a method and apparatus for controlling a plasma sheath near a substrate edge. Changing the voltage/current distribution across the inner electrode and the outer electrode with in the substrate assembly facilitates the spatial distribution of the plasma across the substrate. The method includes providing a first radio frequency power to a central electrode embedded in a substrate support assembly, providing a second radio frequency power to an annular electrode embedded in the substrate support assembly at a location different than the central electrode, wherein the annular electrode circumferentially surrounds the central electrode, monitoring parameters of the first and second radio frequency power, and adjusting one or both of the first and second radio frequency power based on the monitored parameters.
    Type: Application
    Filed: March 8, 2024
    Publication date: July 4, 2024
    Inventors: Edward P. HAMMOND, IV, Jonghoon BAEK
  • Patent number: 11908662
    Abstract: Embodiments described herein relate to apparatus and techniques for radio frequency (RF) phase control in a process chamber. A process volume is defined in the process chamber by a faceplate electrode and a support pedestal. A grounding bowl is disposed within the process chamber about the support pedestal opposite the process volume. The grounding bowl substantially fills a volume other than the process volume below the support pedestal. A phase tuner circuit is coupled to an RF mesh disposed in the support pedestal and the faceplate electrode. The tuner circuit adjusts a phase difference between a phase of the faceplate electrode and a phase of the RF mesh.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Xiaopu Li, Kallol Bera, Edward P. Hammond, IV, Jonghoon Baek, Amit Kumar Bansal, Jun Ma, Satoru Kobayashi
  • Publication number: 20240030305
    Abstract: The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.
    Type: Application
    Filed: May 18, 2023
    Publication date: January 25, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyun LEE, Jonghan LEE, Jonghoon BAEK, Taegon KIM, Yujin JUNG
  • Publication number: 20220406914
    Abstract: A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.
    Type: Application
    Filed: March 10, 2022
    Publication date: December 22, 2022
    Inventors: JAEHYUN LEE, JONGHAN LEE, HYUNGKOO KANG, JONGHOON BAEK
  • Publication number: 20220179328
    Abstract: In some general aspects, a surface of a structure within a chamber of an extreme ultraviolet (EUV) light source is cleaned using a method. The method includes generating a plasma state of a material that is present at a location adjacent to a non-electrically conductive body that is within the chamber. The generation of the plasma state of the material includes electromagnetically inducing an electric current at the location adjacent the non-electrically conductive body to thereby transform the material that is adjacent the non-electrically conductive body from a first state into the plasma state. The plasma state of the material includes plasma particles, at least some of which are free radicals of the material. The method also includes enabling the plasma particles to pass over the structure surface to remove debris from the structure surface without removing the structure from the chamber of the EUV light source.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Chunguang Xia, Jonghoon Baek, John Tom Stewart, IV, Andrew David LaForge, Deniz Van Heijnsbergen, David Robert Evans, Nina Vladimirovna Dziomkina, Yue Ma
  • Patent number: 11347154
    Abstract: In some general aspects, a surface of a structure within a chamber of an extreme ultraviolet (EUV) light source is cleaned using a method. The method includes generating a plasma state of a material that is present at a location adjacent to a non-electrically conductive body that is within the chamber. The generation of the plasma state of the material includes electromagnetically inducing an electric current at the location adjacent the non-electrically conductive body to thereby transform the material that is adjacent the non-electrically conductive body from a first state into the plasma state. The plasma state of the material includes plasma particles, at least some of which are free radicals of the material. The method also includes enabling the plasma particles to pass over the structure surface to remove debris from the structure surface without removing the structure from the chamber of the EUV light source.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 31, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Chunguang Xia, Jonghoon Baek, John Tom Stewart, IV, Andrew David LaForge, Deniz Van Heijnsbergen, David Robert Evans, Nina Vladimirovna Dziomkina, Yue Ma
  • Patent number: 11339475
    Abstract: An apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes are provided. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 24, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Xinhai Han, Deenesh Padhi, Daemian Raj Benjamin Raj, Kristopher Enslow, Wenjiao Wang, Masaki Ogata, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Gregory Eugene Chichkanoff, Shailendra Srivastava, Jonghoon Baek, Zakaria Ibrahimi, Juan Carlos Rocha-Alvarez, Tza-Jing Gung
  • Patent number: 11264482
    Abstract: A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghyun Kim, Inhyun Song, Yeongmin Jeon, Sejin Park, Juyun Park, Jonghoon Baek, Taeyeon Shin, Sooyeon Jeong
  • Publication number: 20210166915
    Abstract: The present disclosure relates to a method and apparatus for controlling a plasma sheath near a substrate edge. Changing the voltage/current distribution across the inner electrode and the outer electrode with in the substrate assembly facilitates the spatial distribution of the plasma across the substrate. The method includes providing a first radio frequency power to a central electrode embedded in a substrate support assembly, providing a second radio frequency power to an annular electrode embedded in the substrate support assembly at a location different than the central electrode, wherein the annular electrode circumferentially surrounds the central electrode, monitoring parameters of the first and second radio frequency power, and adjusting one or both of the first and second radio frequency power based on the monitored parameters.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 3, 2021
    Inventors: Edward P. HAMMOND, IV, Jonghoon BAEK
  • Patent number: 11013096
    Abstract: A system and method of removing target material debris deposits simultaneously with generating EUV light includes generating hydrogen radicals in situ in the EUV vessel, proximate to the target material debris deposits and volatilizing the target material debris deposits and purging the volatilized target material debris deposits from the EUV vessel without the need of an oxygen containing species in the EUV vessel.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 18, 2021
    Assignee: ASML Nettherlands B.V.
    Inventors: Jonghoon Baek, Mathew Cheeran Abraham, David Robert Evans, Jack Michael Gazza
  • Publication number: 20210063899
    Abstract: In some general aspects, a surface of a structure within a chamber of an extreme ultraviolet (EUV) light source is cleaned using a method. The method includes generating a plasma state of a material that is present at a location adjacent to a non-electrically conductive body that is within the chamber. The generation of the plasma state of the material includes electromagnetically inducing an electric current at the location adjacent the non-electrically conductive body to thereby transform the material that is adjacent the non-electrically conductive body from a first state into the plasma state. The plasma state of the material includes plasma particles, at least some of which are free radicals of the material. The method also includes enabling the plasma particles to pass over the structure surface to remove debris from the structure surface without removing the structure from the chamber of the EUV light source.
    Type: Application
    Filed: February 12, 2019
    Publication date: March 4, 2021
    Inventors: Chunguang Xia, Jonghoon Baek, John Tom Stewart, IV, Andrew David LaForge, Deniz Van Heijnsbergen, David Robert Evans, Nina Vladimirovna Dziomkina, Yue MA
  • Publication number: 20200343364
    Abstract: A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.
    Type: Application
    Filed: September 17, 2019
    Publication date: October 29, 2020
    Inventors: Donghyun KIM, Inhyun SONG, Yeongmin JEON, Sejin PARK, Juyun PARK, Jonghoon BAEK, Taeyeon SHIN, Sooyeon JEONG
  • Publication number: 20200173022
    Abstract: Embodiments of the disclosure describe an apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 4, 2020
    Inventors: Xinhai HAN, Deenesh PADHI, Daemian Raj BENJAMIN RAJ, Kristopher ENSLOW, Wenjiao WANG, Masaki OGATA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Gregory Eugene CHICHKANOFF, Shailendra SRIVASTAVA, Jonghoon BAEK, Zakaria IBRAHIMI, Juan Carlos ROCHA-ALVAREZ, Tza-Jing GUNG