Abstract: A general matrix-matrix (GEMM) accelerator core includes first and second buffers, a control logic circuit, and a first processing element (PE). The first buffer receives a elements of a first matrix A of activation values. The second buffer receives b elements of a second matrix B of weight values. The control logic circuit replaces a zero-valued a element in a first column of the first buffer with a nonzero-valued a element that is within a maximum borrowing distance of a location of the zero-valued a element in the first column of the first buffer. The PE receives a elements from the first column of the first buffer including the nonzero-valued element a selected to replace the zero-valued a element and receives b elements from locations in the second buffer that correspond to locations in the first buffer from where the a elements have been received by the PE.

Abstract: An electronic device according to various examples is provided. The electronic device may include a decoder for decoding a compressed video; and a neural processing unit (NPU) for outputting a result frame comprising a first target data in response to searching for the first target data in one or more frames of a first compressed video while the decoder is decoding the first compressed video comprising the one or more frames.

Abstract: A general matrix-matrix (GEMM) accelerator core includes first and second buffers, and a processing element (PE). The first buffer receives a elements of a matrix A of activation values. The second buffer receives b elements of a matrix B of weight values. The matrix B is preprocessed with a nonzero-valued b element replacing a zero-valued b element in a first row of the second buffer based on the zero-valued b element being in the first row of the second buffer. Metadata is generated that includes movement information of the nonzero-valued b element to replace the zero-valued b element. The PE receives b elements from a first row of the second buffer and a elements from the first buffer from locations in the first buffer that correspond to locations in the second buffer from where the b elements have been received by the PE as indicated by the metadata.

Abstract: A core of neural processing units is configured to efficiently process a depthwise convolution by maximizing spatial feature-map locality using adder trees. Data paths of activations and weights are inverted, and 2-to-1 multiplexers are every 2/9 multipliers along a row of multipliers. During a depthwise convolution operation, the core is operated using a RS×HW dataflow to maximize the locality of feature maps. For a normal convolution operation, the data paths of activations and weights may be configured for a normal convolution configuration and in which multiplexers are idle.

Abstract: A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.

Abstract: A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.

Abstract: A system and a method is disclosed for processing input feature map (IFM) data of a current layer of a neural network model using an array of reconfigurable neural processing units (NPUs) and storing output feature map (OFM) data of the next layer of the neural network model at a location that does not involve a data transfer between memories of the NPUs according to the subject matter disclosed herein. The reconfigurable NPUs may be used to improve NPU utilization of NPUs of a neural processing system.

Abstract: An electronic device according to various examples is provided. The electronic device may include a decoder for decoding a compressed video; and a neural processing unit (NPU) for outputting a result frame comprising a first target data in response to searching for the first target data in one or more frames of a first compressed video while the decoder is decoding the first compressed video comprising the one or more frames.

Abstract: A system and method for weight preprocessing. In some embodiments, the method includes performing intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor, and performing inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor. The intra-tile preprocessing may include moving a first element of a first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction. The inter-tile preprocessing may include moving a first row of a weight tile of the first pre-processed weight tensor by one position in a lookahead direction or by one position in a lookaside direction.

Abstract: A distributed power-sharing electric vehicle (EV) charging. The system comprises multiple chargers connected via a network. Each charger includes a power module configured to store direct current (DC) power, an output port for supplying power to an electric vehicle, and a sharing port for exchanging power with at least one neighboring charger. First and second switches are positioned between the power module and the output port, and between the power module and the sharing port. A control unit is configured to control the operation of the power module and the switches in response to an EV charging request. When the maximum charging power required by the EV exceeds the rated output power of a single charger, the system delivers power from both the power module and the neighboring charger in an idle state.

Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: The present disclosure provides a data assimilation system of numerical models using atmospheric research aircraft observation data for constructing a data assimilation system for generating improved initial conditions and performing efficient aerial observation work using atmospheric research aircraft observation data, and a method of constructing a weather prediction model with data assimilation applied of the data assimilation system. A data assimilation system of numerical models using atmospheric research aircraft observation data includes an observation error data generation module, a background error covariance generation module, a data assimilation module and a lateral boundary field generation module.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.

Abstract: A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format.

Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: A distributed power-sharing electric vehicle (EV) charging. The system comprises multiple chargers connected via a network. Each charger includes a power module configured to store direct current (DC) power, an output port for supplying power to an electric vehicle, and a sharing port for exchanging power with at least one neighboring charger. First and second switches are positioned between the power module and the output port, and between the power module and the sharing port. A control unit is configured to control the operation of the power module and the switches in response to an EV charging request. When the maximum charging power required by the EV exceeds the rated output power of a single charger, the system delivers power from both the power module and the neighboring charger in an idle state.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format.

Abstract: A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.