Abstract: A system and method for weight preprocessing. In some embodiments, the method includes performing intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor, and performing inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor. The intra-tile preprocessing may include moving a first element of a first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction. The inter-tile preprocessing may include moving a first row of a weight tile of the first pre-processed weight tensor by one position in a lookahead direction or by one position in a lookaside direction.

Abstract: A distributed power-sharing electric vehicle (EV) charging. The system comprises multiple chargers connected via a network. Each charger includes a power module configured to store direct current (DC) power, an output port for supplying power to an electric vehicle, and a sharing port for exchanging power with at least one neighboring charger. First and second switches are positioned between the power module and the output port, and between the power module and the sharing port. A control unit is configured to control the operation of the power module and the switches in response to an EV charging request. When the maximum charging power required by the EV exceeds the rated output power of a single charger, the system delivers power from both the power module and the neighboring charger in an idle state.

Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: The present disclosure provides a data assimilation system of numerical models using atmospheric research aircraft observation data for constructing a data assimilation system for generating improved initial conditions and performing efficient aerial observation work using atmospheric research aircraft observation data, and a method of constructing a weather prediction model with data assimilation applied of the data assimilation system. A data assimilation system of numerical models using atmospheric research aircraft observation data includes an observation error data generation module, a background error covariance generation module, a data assimilation module and a lateral boundary field generation module.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.

Abstract: A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format.

Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: A distributed power-sharing electric vehicle (EV) charging. The system comprises multiple chargers connected via a network. Each charger includes a power module configured to store direct current (DC) power, an output port for supplying power to an electric vehicle, and a sharing port for exchanging power with at least one neighboring charger. First and second switches are positioned between the power module and the output port, and between the power module and the sharing port. A control unit is configured to control the operation of the power module and the switches in response to an EV charging request. When the maximum charging power required by the EV exceeds the rated output power of a single charger, the system delivers power from both the power module and the neighboring charger in an idle state.

Abstract: An encryption device for performing virtual and real operations and a method of operating the encryption device. The method includes performing a virtual operation; when a real operation request signal is received, determining whether the virtual operation being performed is completed; and in response to the virtual operation being completed, performing a real operation in response to the real operation request signal.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format.

Abstract: A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.

Abstract: A neural processing unit is reconfigurable to process a fine-grain structured sparsity weight arrangement selected from N:M=1:4, 2:4, 2:8 and 4:8 fine-grain structured weight sparsity arrangements. A weight buffer stores weight values and a weight multiplexer array outputs one or more weight values stored in the weight buffer as first operand values based on a selected fine-grain structured sparsity weight arrangement. An activation buffer stores activation values and an activation multiplexer array outputs one or more activation values stored in the activation buffer as second operand values based on the selected fine-grain structured weight sparsity in which each respective second operand value and a corresponding first operand value forms an operand value pair. A multiplier array outputs a product value for each operand value pair.

Abstract: A memory system and a method are disclosed for training a neural network model. A decompressor unit decompresses an activation tensor to a first predetermined sparsity density based on the activation tensor being compressed, and decompresses an weight tensor to a second predetermined sparsity density based on the weight tensor being compressed. A buffer unit receives the activation tensor at the first predetermined sparsity density and the weight tensor at the second predetermined sparsity density. A neural processing unit receives the activation tensor and the weight tensor from the buffer unit and computes a result for the activation tensor and the weight tensor based on first predetermined sparsity density of the activation tensor and based on the second predetermined sparsity density of the weight tensor.

Abstract: A neural network inference accelerator includes first and second neural processing units (NPUs) and a sparsity management unit. The first NPU receives activation and weight tensors based on an activation sparsity density and a weight sparsity density both being greater than a predetermined sparsity density. The second NPU receives activation and weight tensors based on at least one of the activation sparsity density and the weight sparsity density being less than or equal to the predetermined sparsity density. The sparsity management unit controls transfer of the activation tensor and the weight tensor based on the activation sparsity density and the weight sparsity density with respect to the predetermined sparsity density.

Abstract: A neural processing unit is disclosed that supports dual-sparsity modes. A weight buffer is configured to store weight values in an arrangement selected from a structured weight sparsity arrangement or a random weight sparsity arrangement. A weight multiplexer array is configured to output one or more weight values stored in the weight buffer as first operand values based on the selected weight sparsity arrangement. An activation buffer is configured to store activation values. An activation multiplexer array includes inputs to the activation multiplexer array that are coupled to the activation buffer, and is configured to output one or more activation values stored in the activation buffer as second operand values in which each respective second operand value and a corresponding first operand value forming an operand value pair. A multiplier array is configured to output a product value for each operand value pair.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.

Abstract: Provided is a security device, an electronic device, a secure boot management system, a method for generating a boot image and a method for executing a boot chain. The security device includes a key deriver configured to receive a root key and a protected boot key included in a boot image and generate a derived key according to a key protection method using the root key and the protected boot key, a key processor configured to perform verification according to the key protection method using the generated derived key to extract a boot key from the protected boot key included in the boot image, a secure booter configured to perform verification on a protected execution image included in the boot image using the extracted boot key, and a processor configured to execute a verified execution image on which the verification has been completed by the secure booter.