Abstract: An electronic device includes at least one processor, at least one antenna, and a wireless communication circuit electrically connected to the at least one processor and the at least one antenna. The wireless communication circuit includes a switch including a first terminal electrically connected to a path corresponding to a first frequency band, a second terminal electrically connected to a path corresponding to a second frequency band, and a third terminal selectively connected to a corresponding terminal of the first terminal and the second terminal and a filter circuit electrically connected between the third terminal and the at least one antenna and having a designated resonant frequency band. The wireless communication circuit selectively transmits a signal in one corresponding frequency band between the first frequency band and the second frequency band based on a terminal which is connected to the third terminal.

Abstract: An electronic device includes at least one processor, at least one antenna, and a wireless communication circuit electrically connected to the at least one processor and the at least one antenna. The wireless communication circuit includes a switch including a first terminal electrically connected to a path corresponding to a first frequency band, a second terminal electrically connected to a path corresponding to a second frequency band, and a third terminal selectively connected to a corresponding terminal of the first terminal and the second terminal and a filter circuit electrically connected between the third terminal and the at least one antenna and having a designated resonant frequency band. The wireless communication circuit selectively transmits a signal in one corresponding frequency band between the first frequency band and the second frequency band based on a terminal which is connected to the third terminal.

Abstract: According to one embodiment of the present invention, the scheduling method includes an acquisition step of acquiring operation state information on a virtual CPU (vCPU) and lock information on an OS in the operation of the vCPU and of a virtual machine (VM) driving the vCPU and including the OS, and a determination step for determining whether the vCPU is in a lock holder preemption (LHP) state on the basis of the operation state information and the lock information. According to one embodiment of the present invention, the LHP can be easily and precisely known on a system using the VM. Also, even with an increase in the number of cores, scalability can be supported in a system by adjusting the pCPU to which operations of the vCPU are allocated through a scheduling scheme.

Abstract: According to one embodiment of the present invention, the scheduling method includes an acquisition step of acquiring operation state information on a virtual CPU (vCPU) and lock information on an OS in the operation of the vCPU and of a virtual machine (VM) driving the vCPU and including the OS, and a determination step for determining whether the vCPU is in a lock holder preemption (LHP) state on the basis of the operation state information and the lock information. According to one embodiment of the present invention, the LHP can be easily and precisely known on a system using the VM. Also, even with an increase in the number of cores, scalability can be supported in a system by adjusting the pCPU to which operations of the vCPU are allocated through a scheduling scheme.

Abstract: A sample adaptive offset (SAO) processing apparatus reusing an input buffer and an operation method of the SAO processing apparatus may include a SAO parameter parser to parse SAO parameter information from a bitstream; a SAO parameter adjuster to extract SAO type information and offset information from the parsed SAO parameter information; and a filtering performer to perform filtering on the bitstream based on the SAO type information and the offset information.

Abstract: An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering.