Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

Abstract: An electronic component package includes: a first insulation layer; an electronic component mounted in one surface of the first insulation layer; a heat sink formed with a cavity corresponding to the electronic component, bonded to the one surface of the first insulation layer to cover the electronic component, and formed with an inset hole and with an inlet hole; an adhesive charged in the cavity; and a circuit pattern formed in another surface of the first insulation layer.

Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

Abstract: The present invention relates to a method of increasing the expression of a target protein by co-expression of a gene encoding a target protein having a high content of a specific amino acid with a nucleotide sequence encoding the tRNA of the specific amino acid. According to the present invention, the expression of a protein having a high content of a specific amino acid can be remarkably increased by co-expression with the tRNA of the specific amino acid. Thus, the present invention is useful for increasing the productivity of a protein having a high content of a specific amino acid, such as a repetitive protein.

Abstract: A high power Light Emitting Diode (LED) package and a method of producing the same. The high power LED package according to the present invention includes a plurality of light emitting diode chips, a first lead frame with the light emitting diode chips mounted thereon, and a second lead frame disposed at a predetermined interval from the first lead frame. The LED package also includes a package body fixing the first and second lead frames and bonding wires for electrically connecting the plurality of LED chips with upward-inclined inner side walls thereof and a second reflecting part surrounding the entire plurality of LED chips with an upward-inclined inner side wall thereof.

Abstract: The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.

Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

Abstract: A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

Abstract: A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

Abstract: A high power Light Emitting Diode (LED) package and a method of producing the same. The high power LED package according to the present invention includes a plurality of light emitting diode chips, a first lead frame with the light emitting diode chips mounted thereon, and a second lead frame disposed at a predetermined interval from the first lead frame. The LED package also includes a package body fixing the first and second lead frames and bonding wires for electrically connecting the plurality of LED chips. The package body includes at least one first reflecting part separately surrounding each of the plurality of LED chips with upward-inclined inner side walls thereof and a second reflecting part surrounding the entire plurality of LED chips with an upward-inclined inner side wall thereof.

Abstract: A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

Abstract: Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip.

Abstract: Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes.

Abstract: A high power Light Emitting Diode (LED) package and a method of producing the same. The high power LED package according to the present invention includes a plurality of light emitting diode chips, a first lead frame with the light emitting diode chips mounted thereon, and a second lead frame disposed at a predetermined interval from the first lead frame. The LED package also includes a package body fixing the first and second lead frames and bonding wires for electrically connecting the plurality of LED chips. The package body includes at least one first reflecting part separately surrounding each of the plurality of LED chips with upward-inclined inner side walls thereof and a second reflecting part surrounding the entire plurality of LED chips with an upward-inclined inner side wall thereof.

Abstract: Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer.

Abstract: Provided is a semiconductor device including a wafer having an electrode pad; an insulation layer that is formed on the wafer and has an exposure hole exposing the electrode pad; a redistribution layer that is formed on the insulation layer and the exposure hole of the insulation layer and has one end connected to the electrode pad; a conductive post that is formed at the other end of the redistribution layer; an encapsulation layer that is formed on the redistribution layer and the insulation layer such that the upper end portion of the conductive post is exposed; and a solder bump that is formed on the exposed upper portion of the conducive post.

Abstract: A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

Abstract: A surface mounting device-type light emitting diode (SMD-type LED) comprises a package housing one or more pairs of electrodes therein, the package having a predetermined space in the center thereof and a light-emission window which is opened so that light is emitted through the light-emission window; a lens formed on the package so as to cover the light-emission window; an LED chip formed on an electrode inside the package; a wire for electrically connecting the LED chip and the electrode; and a phosphor-mixed layer formed on the surface of the lens adjacent to the light-emission window.

Abstract: An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability.