Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A positive electrode active material for a lithium secondary battery has a mixture of microparticles having a predetermined average particle size (D50) and macroparticles having a larger average particle size (D50) than the microparticles. The microparticles have the average particle size (D50) of 1 to 10 ?m and are at least one selected from the group consisting of particles having a carbon material coating layer on all or part of a surface of primary macroparticles having an average particle size (D50) of 1 ?m or more, particles having a carbon material coating layer on all or part of a surface of secondary particles formed by agglomeration of the primary macroparticles, and a mixture thereof. The macroparticles are secondary particles having an average particle size (D50) of 5 to 20 ?m formed by agglomeration of primary microparticles having a smaller average particle size (D50) than the primary macroparticles.

Abstract: A semiconductor device includes a first fin type pattern in a first region of a substrate. The first fin type pattern includes a plurality of spaced-apart fins having respective sidewalls defined by a first trench. A first gate structure is provided, which intersects the first fin type pattern. A second fin type pattern is provided in a second region of a substrate. The second fin type pattern includes a fin having a sidewall defined by a second trench. A second gate structure is provided, which intersects the second fin type pattern. A field insulating film fills at least a part of the first trench and at least a part of the second trench.

Abstract: A semiconductor device includes a first fin type pattern in a first region of a substrate. The first fin type pattern includes a plurality of spaced-apart fins having respective sidewalls defined by a first trench. A first gate structure is provided, which intersects the first fin type pattern. A second fin type pattern is provided in a second region of a substrate. The second fin type pattern includes a fin having a sidewall defined by a second trench. A second gate structure is provided, which intersects the second fin type pattern. A field insulating film fills at least a part of the first trench and at least a part of the second trench.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A semiconductor device comprises a substrate, a gate structure formed on the substrate, a channel region below the gate structure in the substrate, a first source/drain region and a second source/drain region located at opposite side of the gate structure, a first lightly-doped drain (LDD) junction region formed between the first source/drain region and one end of the channel region, a second lightly-doped drain (LDD) junction region formed between the second source/drain region and the other end of the channel region, a metal silicide layer having a first metal formed on the first and second source/drain regions, an insulating layer formed on the metal silicide layer and the gate structure having a first opening to expose the metal silicide layer, and a conductive layer having the first metal and filling the first opening to contact the metal silicide layer.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A semiconductor device comprises a substrate, a gate structure formed on the substrate, a channel region below the gate structure in the substrate, a first source/drain region and a second source/drain region located at opposite side of the gate structure, a first lightly-doped drain (LDD) junction region formed between the first source/drain region and one end of the channel region, a second lightly-doped drain (LDD) junction region formed between the second source/drain region and the other end of the channel region, a metal silicide layer having a first metal formed on the first and second source/drain regions, an insulating layer formed on the metal silicide layer and the gate structure having a first opening to expose the metal silicide layer, and a conductive layer having the first metal and filling the first opening to contact the metal silicide layer.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.