Patents by Inventor Jong-Kook Kim

Jong-Kook Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970547
    Abstract: The present disclosure relates to a novel anti-HER2 antibody or an antigen-binding fragment thereof used in the prevention or treatment of cancer, a chimeric antigen receptor including the same, and uses thereof. The antibody of the present disclosure is an antibody that specifically binds to HER2 which is highly expressed in cancer cells (particularly, breast cancer or gastric cancer cells), and binds to an epitope that is different from an epitope to which trastuzumab binds.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: April 30, 2024
    Assignee: GC Cell Corporation
    Inventors: Jong Seo Lee, Kyu Tae Kim, Young Ha Lee, In Sik Hwang, Bong Kook Ko, Eunji Choi, You-Sun Kim, Jeongmin Kim, Miyoung Jung, Hoyong Lim, Sungyoo Cho
  • Publication number: 20240130109
    Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 18, 2024
    Inventors: Beom Ho MUN, Eun Jeong KIM, Jong Kook PARK, Seung Mi LEE, Ji Won CHOI, Kyoung Tak KIM, Yun Hyuck JI
  • Patent number: 11950501
    Abstract: An organic light emitting device including: a substrate; a first electrode; a second electrode; and an organic layer interposed between the first electrode and the second electrode and including an emission layer, wherein one of the first electrode and the second electrode is a reflective electrode and the other is a semitransparent or transparent electrode, and wherein the organic layer includes a layer having at least one of the compounds having at least one carbazole group, and a flat panel display device including the organic light emitting device. The organic light emitting device has low driving voltage, excellent current density, high brightness, excellent color purity, high efficiency, and long lifetime.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok-Hwan Hwang, Young-Kook Kim, Yoon-Hyun Kwak, Jong-Hyuk Lee, Kwan-Hee Lee, Min-Seung Chun
  • Patent number: 11936075
    Abstract: Disclosed are a separator for fuel cells capable of minimizing the volume of a system and the use of sealants, and a stack for fuel cells, more particularly, a stack for solid oxide fuel cells, including the same. Specifically, by adding a metal sheet having a specific shape, position and size to the separator, the stress applied to the sealant can be uniformized, and thus the oxidizing agent and fuel can be separated and electrically isolated using only a piece of sealant. Therefore, the stack for fuel cells is characterized in that there is no variation in temperature, reactant concentration, power, or the like between respective unit cells, so delamination and microcracks do not occur, the volume is minimized, and the power density per unit volume is very high.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Korea Institute of Science and Technology
    Inventors: Jong Ho Lee, Kyung Joong Yoon, Ji Won Son, Seong Kook Oh, Sang Hyeok Lee, Dong Hwan Kim, Min Jun Oh
  • Publication number: 20230357598
    Abstract: Provided is a manufacturing method of a stainless steel sheet having etching patterns. The method includes: coating a coating composition on a stainless steel sheet to form a coating layer; and forming a matte coated film layer, having an etching effect, on the coating layer. The coating composition comprises: 10 to 30 wt% of a silane-based compound, 0.5 to 6 wt% of an organic acid, 0.1 to 3 wt% of a vanadium compound, 0.1 to 3 wt% of a magnesium compound, and a remainder of a solvent.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Inventors: Jin-Tae KIM, Ha-Na CHOI, Yang-Ho CHOI, Jung-Hwan LEE, Yon-Kyun SONG, Jong-Kook KIM
  • Patent number: 11063346
    Abstract: Disclosed is a shark fin antenna for a vehicle. The shark fin antenna has a pad and a base disposed on the pad to provide a space for a printed circuit board and a plurality of antenna components. The shark fin antenna includes a holder having a groove therein for exposing at least a portion of an upper surface of a printed circuit board, a first antenna unit supported by the holder and having an antenna pattern formed on a surface thereof to receive an AM/FM frequency band signal, a first auxiliary unit covering at least a portion of an upper surface of the first antenna unit, and a spring mounted in the groove to elastically support the first auxiliary unit and the first antenna unit in a vertical direction of the upper surface of the printed circuit board.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: INFAC ELECS CO., LTD.
    Inventors: Tae Hoon Yang, Sang Hoon Lim, Soo Young Hwang, Ki Seok Uhm, Kyu Chang Nam, Chae Kyun Lim, Jong Kook Kim
  • Publication number: 20210057805
    Abstract: Disclosed is a shark fin antenna for a vehicle. The shark fin antenna has a pad and a base disposed on the pad to provide a space for a printed circuit board and a plurality of antenna components. The shark fin antenna includes a holder having a groove therein for exposing at least a portion of an upper surface of a printed circuit board, a first antenna unit supported by the holder and having an antenna pattern formed on a surface thereof to receive an AM/FM frequency band signal, a first auxiliary unit covering at least a portion of an upper surface of the first antenna unit, and a spring mounted in the groove to elastically support the first auxiliary unit and the first antenna unit in a vertical direction of the upper surface of the printed circuit board.
    Type: Application
    Filed: March 2, 2020
    Publication date: February 25, 2021
    Inventors: Tae Hoon Yang, Sang Hoon Lim, Soo Young Hwang, Ki Seok Uhm, Kyu Chang Nam, Chae Kyun Lim, Jong Kook Kim
  • Publication number: 20200255687
    Abstract: Provided is a coating composition having excellent corrosion resistance and fingerprint resistance, and also provides a stainless steel sheet having etching patterns and a manufacturing method therefor, the stainless steel sheet comprising: a stainless steel sheet; a coating layer, which is formed on the stainless steel sheet and is a cured product of the coating composition; and a quenching coated film layer formed on the coating layer and having a quenching effect, wherein: the coating layer, formed by curing the coating composition having excellent corrosion resistance and fingerprint resistance, is transparent and has high gloss, thereby having an effect of enabling the surface characteristics of the stainless steel sheet to be expressed as they are; the stainless steel sheet having etching patterns has excellent corrosion resistance and fingerprint resistance even on the parts thereof on which the etching patterns are not formed.
    Type: Application
    Filed: November 24, 2016
    Publication date: August 13, 2020
    Inventors: Jin-Tae KIM, Ha-Na CHOI, Yang-Ho CHOI, Jung-Hwan LEE, Yon-Kyun SONG, Jong-Kook KIM
  • Patent number: 10391518
    Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 27, 2019
    Assignee: POSCO
    Inventors: Jin-Tae Kim, Jong-Sang Kim, Bong-Woo Ha, Yang-Ho Choi, Jung-Hwan Lee, Ha-Na Choi, Jong-Kook Kim
  • Patent number: 10056321
    Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-Kyu Kwon, Jong-Kook Kim
  • Publication number: 20170354991
    Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.
    Type: Application
    Filed: August 19, 2015
    Publication date: December 14, 2017
    Inventors: Jin-Tae KIM, Jong-Sang KIM, Bong-Woo HA, Yang-Ho CHOI, Jung-Hwan LEE, Ha-Na CHOI, Jong-Kook KIM
  • Publication number: 20170012025
    Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu KWON, Jong-Kook KIM, Ji-Chul KIM, Byeong-Yeon CHO
  • Patent number: 9349713
    Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Kook Kim, Byoung-Wook Jang
  • Publication number: 20160027764
    Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.
    Type: Application
    Filed: March 25, 2015
    Publication date: January 28, 2016
    Inventors: Jong-Kook KIM, Byoung-Wook JANG
  • Patent number: 9129826
    Abstract: In a semiconductor assembly having stacked elements, discrete bumps made of a polymer such as an electrically nonconductive epoxy are interposed between the upper surface of a substrate and the lower surface of the overhanging part of an elevated element (die or package) with the discrete bump directly under bond sites on the elevated element.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 8, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, Chul Sik Kim, Ki Youn Jang
  • Publication number: 20150051728
    Abstract: Provided is a detecting method of abnormality of a machine tool operation, and the detecting method includes a preparing step S100; a reference waveform obtaining step S200 of measuring a drive voltage and a drive current, while machining the material in a normal state of the machine tool, and obtaining a reference waveform; a monitoring section setting step S300 of setting a monitoring section and thus automatically calculating a maximum load value and a minimum load value; a permissible limit setting step S400 of setting maximum and minimum permissible limits; and a monitoring step S500 of obtaining a machining load generated and determining whether a difference between maximum and minimum load values of the machining load is out of the maximum or minimum permissive limit and then outputting normality or abnormality thereof.
    Type: Application
    Filed: December 12, 2013
    Publication date: February 19, 2015
    Applicants: KOREA TOOL MONITORING CO., LTD., DASAN TOOL CO., LTD.
    Inventors: Byung-Hak KIM, Jong-Kook KIM
  • Publication number: 20140312489
    Abstract: A flip-chip semiconductor package is provided that includes a semiconductor chip, a package substrate having a chip attachment surface on which bond sites are formed, and bumps attached to an active surface of the semiconductor chip and bonded to the bond sites, wherein the bond sites are radially arranged around a middle portion of the package substrate.
    Type: Application
    Filed: January 15, 2014
    Publication date: October 23, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: HO-HYEUK IM, JONG-KOOK KIM, SU-MIN PARK
  • Publication number: 20140159237
    Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.
    Type: Application
    Filed: October 31, 2013
    Publication date: June 12, 2014
    Inventors: Heung-Kyu KWON, Jong-Kook KIM
  • Publication number: 20130256916
    Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.
    Type: Application
    Filed: February 1, 2013
    Publication date: October 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-Kyu KWON, Jong-Kook KIM, Ji-Chul KIM, Byeong-Yeon CHO
  • Patent number: 8519517
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang