Abstract: The present invention relates to: a solution composition capable of improving corrosion-resistance and blackening-resistance of a steel sheet; sheet surface-treated using same; and a method for manufacturing the steel sheet.

Abstract: Provided is a manufacturing method of a stainless steel sheet having etching patterns. The method includes: coating a coating composition on a stainless steel sheet to form a coating layer; and forming a matte coated film layer, having an etching effect, on the coating layer. The coating composition comprises: 10 to 30 wt % of a silane-based compound, 0.5 to 6 wt % of an organic acid, 0.1 to 3 wt % of a vanadium compound, 0.1 to 3 wt % of a magnesium compound, and a remainder of a solvent.

Abstract: Provided is a manufacturing method of a stainless steel sheet having etching patterns. The method includes: coating a coating composition on a stainless steel sheet to form a coating layer; and forming a matte coated film layer, having an etching effect, on the coating layer. The coating composition comprises: 10 to 30 wt% of a silane-based compound, 0.5 to 6 wt% of an organic acid, 0.1 to 3 wt% of a vanadium compound, 0.1 to 3 wt% of a magnesium compound, and a remainder of a solvent.

Abstract: Provided is a coating composition having excellent corrosion resistance and fingerprint resistance, and also provides a stainless steel sheet having etching patterns and a manufacturing method therefor, the stainless steel sheet comprising: a stainless steel sheet; a coating layer, which is formed on the stainless steel sheet and is a cured product of the coating composition; and a quenching coated film layer formed on the coating layer and having a quenching effect, wherein: the coating layer, formed by curing the coating composition having excellent corrosion resistance and fingerprint resistance, is transparent and has high gloss, thereby having an effect of enabling the surface characteristics of the stainless steel sheet to be expressed as they are; the stainless steel sheet having etching patterns has excellent corrosion resistance and fingerprint resistance even on the parts thereof on which the etching patterns are not formed.

Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.

Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.

Abstract: A method of manufacturing a transparent pattern printed steel plate includes forming a printed paint film layer by jetting transparent ink onto at least one surface of a steel plate, and curing the printed paint film layer with ultraviolet light to form a cured printed paint film layer. Further, a method of manufacturing a transparent pattern printed steel plate includes preparing a steel plate having a color painted film layer formed on at least one surface thereof, forming a printed paint film layer by jetting transparent ink onto the color painted film layer, and curing the printed paint film layer to form a cured printed paint film layer.

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.

Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.

Abstract: Provided is a detecting method of abnormality of a machine tool operation, and the detecting method includes a preparing step S100; a reference waveform obtaining step S200 of measuring a drive voltage and a drive current, while machining the material in a normal state of the machine tool, and obtaining a reference waveform; a monitoring section setting step S300 of setting a monitoring section and thus automatically calculating a maximum load value and a minimum load value; a permissible limit setting step S400 of setting maximum and minimum permissible limits; and a monitoring step S500 of obtaining a machining load generated and determining whether a difference between maximum and minimum load values of the machining load is out of the maximum or minimum permissive limit and then outputting normality or abnormality thereof.

Abstract: A flip-chip semiconductor package is provided that includes a semiconductor chip, a package substrate having a chip attachment surface on which bond sites are formed, and bumps attached to an active surface of the semiconductor chip and bonded to the bond sites, wherein the bond sites are radially arranged around a middle portion of the package substrate.

Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.

Abstract: Disclosed is a functional shoe, comprising a foot arch support, wherein said foot arch support includes a support body accommodated and fixed in a shoe body, a slider tightened to the support body by a screw, and a contact member which is coupled to the top of the slider and projects toward the inside of the shoe to contact the arch of the foot. The slider moves in the upward and downward directions by means of the rotation of the contact member.

Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.

Abstract: An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern.

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.