Patents by Inventor Jongkook Lee

Jongkook Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006188
    Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
  • Patent number: 10431522
    Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
  • Publication number: 20190139899
    Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonha JUNG, Jongkook KIM, Bona BAEK, Heeseok LEE, Kyoungsei CHOI
  • Patent number: 9641013
    Abstract: A method of balancing rack voltages of a battery pack having a plurality of racks includes (a) a voltage measurement step of measuring voltages of the racks, (b) a sorting step of sorting the racks in ascending powers based on the voltage values of the racks, (c) a comparison step of comparing a difference between a maximum voltage value and a minimum voltage value with a set voltage, (d) a charging/discharging count step of comparing the voltage values of the racks with a reference voltage to increase a charging or discharging count, and (e) a charging/discharging step of charging or discharging the racks according to the charging or discharging count. In a case in which, at step (c), the difference between the maximum voltage value and the minimum voltage value is lower than the set voltage, the racks are charged with the maximum voltage value without steps (d) and (c).
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: May 2, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Jongkook Lee, Hyunchul Lee, Jongmin Park
  • Publication number: 20160172875
    Abstract: Disclosed herein is a method of balancing rack voltages of a battery pack configured to have a structure in which a plurality of racks is connected in series or in parallel to each other, and a plurality of unit modules is connected in series to each other in each of the racks, the rack voltage balancing method including (a) a voltage measurement step of measuring voltages of the racks, (b) an sorting step of sorting the racks in ascending powers based on the voltage values of the racks, (c) a comparison step of comparing a difference between a maximum voltage value and a minimum voltage value with a set voltage, (d) a charging/discharging count step of comparing the voltage values of the racks with a reference voltage to increase a charging or discharging count, and (e) a charging/discharging step of charging or discharging the racks according to the charging or discharging count, wherein, in a case in which, at step (c), the difference between the maximum voltage value and the minimum voltage value is lower
    Type: Application
    Filed: August 12, 2014
    Publication date: June 16, 2016
    Applicant: LG CHEM, LTD.
    Inventors: Jongkook LEE, Hyunchul LEE, Jongmin PARK
  • Publication number: 20080208962
    Abstract: Disclosed are a real time automatic update system and method for disaster damage investigation using wireless communication and a web-GIS (Geographic Information System), which are able to prevent disaster recurrence by effectively acquiring various data associated with a disaster area in disaster investigation, quickly establish a disaster register and enable easy searching by loading corresponding data on the web.
    Type: Application
    Filed: May 24, 2007
    Publication date: August 28, 2008
    Applicants: INHA-INDUSTRY PARTNERSHIP INSTITUTE, DATA PCS CO., LTD
    Inventors: Kyehyun Kim, Jongkook Lee
  • Patent number: 7022839
    Abstract: The present invention relates to heterodimeric conjugates of neomycin-chloramphenicol, of formula 1, their preparation and their use. Because of their heterodmieric structure, they can recognize both stem and loop of RNA motif and show binding ability to a certain RNA such that they have an enhanced pharmaceutical efficacy and reduced side effect which can be caused by non-specific drugs. For these reasons, they can be effectively used as an antiviral agent, an antibacterial agent or an anticancer drugs.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: April 4, 2006
    Assignee: Korea Institute of Science and Technology
    Inventors: Jaehoon Yu, Jongkook Lee, Miyun Kwon, Kye-Jung Shin
  • Publication number: 20050222055
    Abstract: The present invention relates to novel oxazolidinone derivatives represented as following compound I and a process for the preparation thereof. The compounds of the present invention have wide antibacterial spectrums superior antibacterial activity and low toxicity. Therefore, it can be expected to use as novel antibacterial agent. wherein, R1 is alkylcarboxyl group or —CH2R2 (wherein, R2 is OH, argido group, —OR3 (wherein, R3 is C1-4 alkyl, methansulfonyl, p-toluensulfonyl, carboxyl, C1-4 alkylcarboxyl, C1-4 alkylcarbonyl, benzyloxycarbonyl, or imidazolylcarbonyl), or —NHR4).
    Type: Application
    Filed: July 4, 2002
    Publication date: October 6, 2005
    Inventors: Jaehoon Yu, Jongkook Lee, Miyun Kwon, Ae Pae, Hun Koh
  • Publication number: 20050009765
    Abstract: The present invention relates to heterodimeric conjugates of neomycin-chloramphenicol of formula 1, their preparation and their use. Because of their heterodimeric structure, they can recognize both stem and loop of RNA motif and show binding ability to a certain RNA such that they have an enhanced pharmaceutical efficacy and reduced side effect which can be caused by non-specific drugs. For these reasons, the can be effectively used as an antiviral agent, an antibacterial agent or an anti cancer drugs.
    Type: Application
    Filed: December 5, 2001
    Publication date: January 13, 2005
    Inventors: Jaehoon Yu, Jongkook Lee, Miyun Kwon, Kye-Jung Shin