Abstract: The present invention extends to methods, systems, and computer program products for dynamically throttling host write data rates, for example, at SSDs. Host write data is received from a host at a host write data rate. The host write data is buffered in an SSD buffer at the host write data rate. Some host write data is transferred from the SSD buffer to NAND storage at an internal NAND data rate. A host write throttle is calculated at least based on the host data rate and the internal NAND data rate. The host write throttle defines a new (e.g., increased or decreased) host write data rate. The host write throttle is sent to the host requesting the host utilize the new host write data rate. When a new host write data rate is decreased, data transfer from SSD buffer to NAND storage can be allowed to “catch up”.

Abstract: The present invention extends to methods, systems, and computer program products for dynamically throttling host write data rates, for example, at SSDs. Host write data is received from a host at a host write data rate. The host write data is buffered in an SSD buffer at the host write data rate. Some host write data is transferred from the SSD buffer to NAND storage at an internal NAND data rate. A host write throttle is calculated at least based on the host data rate and the internal NAND data rate. The host write throttle defines a new (e.g., increased or decreased) host write data rate. The host write throttle is sent to the host requesting the host utilize the new host write data rate. When a new host write data rate is decreased, data transfer from SSD buffer to NAND storage can be allowed to “catch up”.

Abstract: A peripheral device implements a plurality of queue sets each including a submission queue and a completion queue. Changes to the queues are monitored and arbitration parameters are adjusted, the arbitration parameters defining how submission queues are selected for retrieval of a command. An arbitration burst for a submission queue may be increased in response to tail movement for the submission queue being larger than for another submission queue. Priorities used for weighted round robin arbitration may also be adjusted based on tail movement. Arbitration burst quantities and priorities of groups of queues may also be adjusted. Head movement of the completion queues is monitored and may be used to lower priority, enable interrupt coalescing, or pause command retrieval where head movement does not meet a threshold condition.

Abstract: A peripheral device implements a plurality of queue sets each including a submission queue and a completion queue. Changes to the queues are monitored and arbitration parameters are adjusted, the arbitration parameters defining how submission queues are selected for retrieval of a command. An arbitration burst for a submission queue may be increased in response to tail movement for the submission queue being larger than for another submission queue. Priorities used for weighted round robin arbitration may also be adjusted based on tail movement. Arbitration burst quantities and priorities of groups of queues may also be adjusted. Head movement of the completion queues is monitored and may be used to lower priority, enable interrupt coalescing, or pause command retrieval where head movement does not meet a threshold condition.

Abstract: A storage device implements striping logic with respect to a plurality of slices, each slice including one or more storage media, such as NAND flash dies. Data operations are distributed among the slice in an unequal manner such that the frequency of selection of a slice decreases with number of defects in the NAND dies of that slice. For example, data operations may be distributed in a round-robin fashion with some slices being skipped periodically. In some embodiments, a skip map may be used that maps host addresses (HLBA) to a particular slice and device address (DLBA) in that slice, the skip map implementing the skipping of slices. The skip map may be smaller than the size of the storage device such that each HLBA is mapped to a zone of the storage device and a slice and offset within that zone are determined according to the skip map.

Abstract: A storage device implements striping logic with respect to a plurality of slices, each slice including one or more storage media, such as NAND flash dies. Data operations are distributed among the slice in an unequal manner such that the frequency of selection of a slice decreases with number of defects in the NAND dies of that slice. For example, data operations may be distributed in a round-robin fashion with some slices being skipped periodically. In some embodiments, a skip map may be used that maps host addresses (HLBA) to a particular slice and device address (DLBA) in that slice, the skip map implementing the skipping of slices. The skip map may be smaller than the size of the storage device such that each HLBA is mapped to a zone of the storage device and a slice and offset within that zone are determined according to the skip map.

Abstract: A storage device retrieves commands from a command queue of a host and monitors depth of the command queue. Commands are executed from the command queue and outcomes of the commands are written to a completion queue of the host. Interrupts for the completed commands are coalesced until an aggregation threshold or aggregation delay are met. Coalescing is disabled and interrupts generated upon completion of commands when depth of the command queue is below a threshold.

Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.

Abstract: A storage device, such as a NAND flash device, avoids the need for garbage collection. An application executing on a host system tracks data objects that are marked as invalid and maintains an association between data objects and logical blocks, each logical block corresponding to a physical block of memory in the NAND flash device. Upon determining that the logical block contains no valid objects, the application instructs an SSD to trim the physical block of memory corresponding to the logical block. The application also aggregates write commands until a full block of data is ready to be written, at which point the application transmits a write command to the SSD.

Abstract: A storage device, such as a NAND flash device, includes a controller that maintains a temperature for a plurality of data blocks, the temperature calculated according to a function that increases with a number of valid data objects in the block and recency with which the valid data objects have been accessed. Blocks with the lowest temperature are selected for garbage collection. Recency for a block is determined based on a number of valid data objects stored in the block that are referenced in a hot list of a LRU list. During garbage collection, data objects that are least recently used are invalidated to reduce write amplification.

Abstract: A storage device, such as a NAND flash device, avoids the need for garbage collection. An application executing on a host system tracks data objects that are marked as invalid and maintains an association between data objects and logical blocks, each logical block corresponding to a physical block of memory in the NAND flash device. Upon determining that the logical block contains no valid objects, the application instructs an SSD to trim the physical block of memory corresponding to the logical block. The application also aggregates write commands until a full block of data is ready to be written, at which point the application transmits a write command to the SSD.

Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.

Abstract: A storage device, such as a NAND flash device, includes a controller that maintains a temperature for a plurality of data blocks, the temperature calculated according to a function that increases with a number of valid data objects in the block and recency with which the valid data objects have been accessed. Blocks with the lowest temperature are selected for garbage collection. Recency for a block is determined based on a number of valid data objects stored in the block that are referenced in a hot list of a LRU list. During garbage collection, data objects that are least recently used are invalidated to reduce write amplification.