Abstract: An apparatus including a switch may include a first interface configured to communicate with at least one memory device, and a second interface configured to communicate with a first physical connector and a second physical connector, where the switch is configured to communicate with a device using the first physical connector using a memory access protocol. The second interface may be configured to communicate with a second device using the second physical connector using the memory access protocol. The apparatus may further include a second switch including a third interface configured to communicate with the at least one memory device, and a fourth interface configured to communicate with a third physical connector and a fourth physical connector, where the second switch may be configured to communicate with the device using the third physical connector using the memory access protocol.

Abstract: A system may include a memory device including memory media and storage media, wherein the memory device is configured to perform one or more operations including sending access information; receiving address information; and populating, from the storage media, the memory media with data using the address information; and a device including one or more circuits, wherein the one or more circuits is configured to perform one or more operations including receiving, from the memory device, the access information; determining, using the access information and application weights, the address information; and sending, to the memory device, the address information. The one or more circuits may be further configured to perform one or more operations including sending, to a training system, trace information; receiving a weight set from the training system, wherein the weight set is based on the trace information; and modifying the application weights based on the weight set.

Abstract: A system and method for page mirroring for storage. In some embodiments, the method includes: reading first data from a persistent memory device; establishing that the first data is stored in a first cache; and copying the first data from the first cache to a system memory, wherein the persistent memory device supports an external protocol and a memory protocol.

Abstract: A method may include receiving a request for a memory page in a memory tier comprising a first memory device and a second memory device, wherein the first memory device has a first parameter and the second memory device has a second parameter, selecting, based on the first parameter and the second parameter, the first memory device, and allocating, based on the request, based on the selecting, the memory page from the first memory device. The selecting may include determining a first result based on the first parameter, determining a second result based on the second parameter, and comparing the first result and the second result. The determining the first result may include combining the first parameter with a first weight. The first weight may include a first scale factor, and the combining the first parameter with the first weight may include multiplying the first parameter and the first scale factor.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A system and method for fault page handling. In some embodiments, the method includes: querying a memory device for fault pages in the memory device; and receiving a response from the memory device identifying a fault page. The querying of the memory device may include querying the memory device by a device driver; and the querying of the memory device may include querying the memory device using a supplemental command of a cache coherent protocol.

Abstract: A system for handling faulty pages includes: a host processor; host memory connected to the host processor over a first memory interface; and an expandable memory pool connected to the host processor over a second memory interface different from the first memory interface. The host memory includes instructions that, when executed by the host processor, cause the host processor to: detect an error in a target page of a first memory device of the expandable memory pool; generate an interrupt in response to detecting the error; store in a faulty page log, faulty page information corresponding to the target page of the first memory device; and change a status of the target page of the first memory device from a first state to a second state according to the faulty page log.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A system for handling faulty pages, including: a host processor; host memory connected to the host processor over a first memory interface; and an expandable memory pool connected to the host processor over a second memory interface different from the first memory interface, the host memory including instructions that, when executed by the host processor, cause the host processor to: detect an error in a target page of a first memory device of the expandable memory pool; generate an interrupt in response to detecting the error; store in a faulty page log, faulty page information corresponding to the target page of the first memory device; and change a status of the target page of the first memory device from a first state to a second state according to the faulty page log.

Abstract: A method may include receiving a request for a memory page in a memory tier comprising a first memory device and a second memory device, wherein the first memory device has a first parameter and the second memory device has a second parameter, selecting, based on the first parameter and the second parameter, the first memory device, and allocating, based on the request, based on the selecting, the memory page from the first memory device. The selecting may include determining a first result based on the first parameter, determining a second result based on the second parameter, and comparing the first result and the second result. The determining the first result may include combining the first parameter with a first weight. The first weight may include a first scale factor, and the combining the first parameter with the first weight may include multiplying the first parameter and the first scale factor.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A database offloading engine. In some embodiments, the database offloading engine includes a vectorized adder including a plurality of read-modify-write circuits, a plurality of sum buffers respectively connected to the read-modify-write circuits, a key address table, and a control circuit. The control circuit may be configured to receive a first key and a corresponding first value; to search the key address table for the first key; and, in response to finding, in the key address table, an address corresponding to the first key, to route the address and the first value to a read-modify-write circuit, of the plurality of read-modify-write circuits, corresponding to the address.

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Abstract: A method of retrieving data stored in a memory associated with a dedupe module is provided. The method includes: identifying a logical address of the data; identifying a physical line ID of the data in accordance with the logical address by looking up at least a portion of the logical address in a translation table; locating a respective physical line, the respective physical line corresponding to the PLID; and retrieving the data from the respective physical line, the retrieving including copying a respective hash cylinder to the read cache, the respective hash cylinder including: a respective hash bucket, the respective hash bucket including the respective physical line; and a respective reference counter bucket, the respective reference counter bucket including a respective reference counter associated with the respective physical line.

Abstract: A database offloading engine. In some embodiments, the database offloading engine includes a vectorized adder including a plurality of read-modify-write circuits, a plurality of sum buffers respectively connected to the read-modify-write circuits, a key address table, and a control circuit. The control circuit may be configured to receive a first key and a corresponding first value; to search the key address table for the first key; and, in response to finding, in the key address table, an address corresponding to the first key, to route the address and the first value to a read-modify-write circuit, of the plurality of read-modify-write circuits, corresponding to the address.

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Abstract: A dedupe module is provided. The dedupe module includes: a host interface; a dedupe engine to receive a data request from a host system via the host interface; a memory controller; a plurality of memory modules, each memory module being coupled to the memory controller; and a read cache for caching data from the memory controller for use by the dedupe engine.

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.