Abstract: A semiconductor memory device comprises a storage pad on a substrate, a lower electrode structure on the storage pad, an upper support pattern on the lower electrode structure opposite the storage pad, a capacitor dielectric film on the lower electrode structure and the upper support pattern, and an upper electrode on the capacitor dielectric film, wherein the lower electrode structure includes a first lower electrode, a second lower electrode, and a third lower electrode, the second lower electrode is between the first lower electrode and the third lower electrode, and the third lower electrode extends on an upper face of the first lower electrode and an upper face of the second lower electrode that are opposite the storage pad.

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

Abstract: A semiconductor device includes a first interlayer insulating layer on a substrate and including an upper surface at a first level, a second interlayer insulating layer on the first interlayer insulating layer, and including a material with less density than that of the first interlayer insulating layer, a first contact in the first interlayer insulating layer and having an upper surface at a second level higher than the first level, a through via in the first interlayer insulating layer and substrate, and having an upper surface at a third level higher than the second level, a first wiring in the second interlayer insulating layer, in contact with the first contact, and having a lower surface at a fourth level lower than the first level, and a second wiring in the second interlayer insulating layer, in contact with the through via, and having a fifth level lower than the fourth level.

Abstract: A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad. Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

Abstract: Provided is a semiconductor package, including a semiconductor substrate including a plurality of first vias, a chip stack on the semiconductor substrate, the chip stack including first semiconductor chips on the semiconductor substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, and a mold layer on the semiconductor substrate and the chip stack, and exposing a top surface of the chip stack, wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips, wherein the semiconductor substrate further includes lower substrate pads on a bottom surface of the semiconductor substrate, wherein each of the first semiconductor chips includes lower chip pads on a bottom surface of each of the first semiconductor chips, and wherein a first width

Abstract: An object of the present disclosure is to provide a composition for preventing or treating obesity comprising a substance isolated from poly-?-glutamic acid (?-PGA) as an active ingredient. According to the present disclosure, it was confirmed that ?-PGAbm or ?-PGAcm, a substance isolated from ?-PGA, suppressed the expression of adipogenic marker genes in 3T3-L1 cells to reduce accumulation of lipid droplets and triglycerides, and suppressed the expression of cell cycle regulators in the early stage of adipogenesis to reduce adipocyte differentiation. In addition, ?-PGAbm or ?-PGAcm has been confirmed to suppress obesity through weight loss, positive changes in glucose and insulin resistance, reduction of epididymal adipocytes, and suppression of adipogenesis, and thus may be used effectively for related businesses.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: The semiconductor device is provided. The semiconductor device comprises a substrate; a plurality of lower electrodes on the substrate and arranged in a honeycomb structure; and a supporter connecting the plurality of lower electrodes to each other, wherein the supporter has a plurality of supporter holes defined therein, wherein each of the plurality of supporter holes exposes at least a portion of each of the plurality of lower electrodes, wherein the supporter includes: a plurality of first extensions extending in a first direction; and a plurality of second extensions extending in a second direction so as to intersect the plurality of first extensions, wherein each of the plurality of first extensions has first and second sidewalls, wherein each of the plurality of second extensions has third and fourth sidewalls, wherein each of the first to fourth sidewalls includes a convex portion and a concave portion.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for: selecting error-prone pages each having a number of errors, which exceeds a threshold, among the plurality of pages, based on the number of errors of each of the plurality of pages; ranking the error-prone pages based on the numbers of errors therein; and performing a test read operation on the error-prone pages based on the ranking.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each including a plurality of memory cells coupled to a plurality of word lines, and a controller configured to determine an operation status regarding a selected memory block among the plurality of memory blocks by performing read test operations to the selected memory block in stages. During the read test operations, the controller adjusts the numbers of word lines selected in each of the stages, based on an error.

Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Abstract: A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.