Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a plurality of grains and grain boundaries disposed between adjacent grains. The grain boundary includes a secondary phase including Sn, a rare-earth element, and a first subcomponent. The rare-earth element includes at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd and Yb. The first subcomponent includes at least one of Si, Mg, and Al.

Abstract: The present disclosure relates to a composite membrane in which a rubbery polymer is introduced into a gutter layer to suppress the physical aging of the highly permeable composite membrane, and more particularly, to a composite membrane comprising a porous support layer; a gutter layer on the porous support layer; and an active layer on the gutter layer, wherein the gutter layer comprises a blend of poly(l-trimethlsilyl-l-propyne) (PTMSP) and a rubbery polymer and a method for preparing the same. The composite membrane according to the present disclosure has high permeation performance and a remarkable decline in physical aging leading to a decrease in permeability over time and thus has very high industrial applicability.

Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.

Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.

Abstract: A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Abstract: A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate.

Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.