Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

Abstract: In certain aspects, a method for providing electrical stimulation includes transferring energy from a battery to an electrode to charge the electrode, and, after the electrode is charged, transferring energy from the electrode to the battery to discharge the battery. The energy transferred from the electrode to the battery may include a portion of the energy transferred from the battery to the electrode.

Abstract: In certain aspects, a method for providing electrical stimulation includes transferring energy from a battery to an electrode to charge the electrode, and, after the electrode is charged, transferring energy from the electrode to the battery to discharge the battery. The energy transferred from the electrode to the battery may include a portion of the energy transferred from the battery to the electrode.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for adjusting voltage regulators of a power supply, such as an envelope tracking power supply. Certain aspects provide a power supply. The power supply may include a first voltage regulator having an output coupled to a voltage supply node of an amplifier. The power supply may further include a second voltage regulator having an output coupled to the voltage supply node of the amplifier. The power supply may further include a controller for adjusting a ratio of an average current supplied by the first voltage regulator to an average current supplied by the second voltage regulator to the voltage supply node of the amplifier based on an output voltage supplied to the voltage supply node of the amplifier by the first voltage regulator and the second voltage regulator.

Abstract: The present disclosure includes circuits that have a switching regulator and methods of operating the circuits. The switching regulator may receive a switching signal that has a switching frequency. The circuit also includes a monitor circuit to monitor the switching frequency, and includes a reconfigurable inductance coupled to an output of the switching regulator. The monitor circuit may change the reconfigurable inductance. The circuit includes an amplifier to receive an envelope tracking signal. An output of the amplifier is coupled to the output of the switching regulator to provide a power supply voltage. The circuit may further include a switching generator circuit to produce the switching signal for the switching regulator based on an output current of the amplifier. The monitor circuit may compare a frequency of the envelope tracking signal to the switching frequency of the switching signal and accordingly change the reconfigurable inductance.

Abstract: The present disclosure includes multi-level switching regulator circuits and methods with finite state machine control. In one embodiment, a circuit comprises a switching regulator and a finite state machine. The switching regulator comprises high side and low side switches, and at least one capacitor. A finite state machine receiving a switching signal and a duty cycle signal to generate switch control signals to the switches. The switches are turned on and off under control of the finite state machine in response to transitions of the switching signal and the duty cycle signal. The switching signal may be generated from an envelope tracking signal, and the switching regulator may be part of an envelope tracking system.

Abstract: The present disclosure includes switching regulator circuits and methods having reconfigurable inductance. In one embodiment, a circuit comprises a switching regulator, the switching regulator receiving a switching signal having a switching frequency, a monitor circuit to monitor the switching frequency, and a reconfigurable inductance at an output of the switching regulator, wherein the monitor circuit changes the reconfigurable inductance between a plurality of inductance values based on the switching frequency. In envelope tracking applications, an envelope tracking signal frequency and switching frequency are monitored to adjust a switching stage inductance.

Abstract: The present disclosure includes multi-level switching regulator circuits and methods with finite state machine control. In one embodiment, a circuit comprises a switching regulator and a finite state machine. The switching regulator comprises high side and low side switches, and at least one capacitor. A finite state machine receiving a switching signal and a duty cycle signal to generate switch control signals to the switches. The switches are turned on and off under control of the finite state machine in response to transitions of the switching signal and the duty cycle signal. The switching signal may be generated from an envelope tracking signal, and the switching regulator may be part of an envelope tracking system.

Abstract: The present disclosure includes envelope tracking circuits and methods with adaptive switching frequency. In one embodiment, a circuit comprising an amplifier to receive an envelope tracking signal having an envelope tracking frequency and output voltage and current to a power supply terminal of a power amplifier circuit. A programmable comparator receives an output signal from the amplifier and generates a switching signal having a switching frequency. A switching regulator stage receives the switching signal and outputs a switching current to the power supply terminal. A frequency comparison circuit configures the programmable comparator based on the envelope tracking frequency and the switching frequency so that the switching frequency tracks the envelope tracking frequency.

Abstract: A method of reading data is provided. The method includes receiving an analog signal, converting the analog signal to a one bit wide digital signal at a first sampling frequency, and downsampling the digital signal to provide the one bit wide digital signal at a second sampling frequency. The method further includes conditioning the digital signal prior to providing the digital signal to the detector. The conditioning can be performed after downsampling the digital signal. A data communication channel is also provided. The data communication channel includes an analog to digital converter configured to provide a first one bit wide digital data stream at a first sampling frequency and a signal conditioning member configured to accept the first one bit wide digital data stream at a first sampling frequency and provide a second one bit wide digital data stream at a second sampling frequency.

Abstract: A method of reading data is provided. The method includes receiving an analog signal, converting the analog signal to a one bit wide digital signal at a first sampling frequency, and downsampling the digital signal to provide the one bit wide digital signal at a second sampling frequency. The method further includes conditioning the digital signal prior to providing the digital signal to the detector. The conditioning can be performed after downsampling the digital signal. A data communication channel is also provided. The data communication channel includes an analog to digital converter configured to provide a first one bit wide digital data stream at a first sampling frequency and a signal conditioning member configured to accept the first one bit wide digital data stream at a first sampling frequency and provide a second one bit wide digital data stream at a second sampling frequency.