Patents by Inventor Jong-Seon Ahn

Jong-Seon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7585757
    Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
  • Publication number: 20080087933
    Abstract: Example embodiments relate to a semiconductor memory device including a channel layer pattern on a substrate, the channel layer pattern having a sidewall and an upper face, a spacer on the sidewall of the channel layer pattern, and a gate electrode covering the sidewall of the channel layer pattern, the spacer and the upper face of the channel layer pattern.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 17, 2008
    Inventors: Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Jong-Seon Ahn
  • Publication number: 20070281434
    Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.
    Type: Application
    Filed: August 20, 2007
    Publication date: December 6, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Seon AHN, Joon KIM, Suk-Chul BANG, Sang-Hoon LEE, Yung-Jun KIM, Woo-Soon JANG, Eun-Kuk CHUNG
  • Publication number: 20060281290
    Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 14, 2006
    Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
  • Publication number: 20050110143
    Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.
    Type: Application
    Filed: November 19, 2004
    Publication date: May 26, 2005
    Inventors: Jong-Seon Ahn, Joon Kim, Suk Bang, Sang-Hoon Lee, Yung-Jun Kim, Woo-Soon Jang, Eun-Kuk Chung