Abstract: An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction.

Abstract: An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction.

Abstract: An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction.

Abstract: The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300) for constructing an integrated circuit.

Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Abstract: The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300 ) for constructing an integrated circuit.

Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).