Abstract: An ion beam source apparatus may include: a plasma chamber configured to generate plasma; and a slit structure configured to extract an ion beam from the plasma and radiate the ion beam toward a wafer, wherein the slit structure includes: a plasma plate on a side of the plasma chamber, the plasma plate including at least one opening through which the ion beam passes; at least one blocking bar within the plasma chamber, the at least one blocking bar spaced apart from the at least one opening by a gap, the gap being between the plasma plate and the at least one blocking bar in a first direction; and a lift structure connected to the at least one blocking bar, the lift structure configured to control an angle at which the ion beam passing through the at least one opening is radiated by adjusting the gap between the plasma plate and the at least one blocking bar in the first direction.

Abstract: An integrated circuit device includes a lower insulating film on a substrate, a lower metal wiring layer extending through the lower insulating film, an insulating protective structure on a top surface of each of the lower metal wiring layer and the lower insulating film, an upper insulating film on the insulating protective structure, an upper metal wiring layer on the upper insulating film, and a conductive contact plug extending through the upper insulating film and the insulating protective structure in a vertical direction and contacting each of the lower metal wiring layer and the upper metal wiring layer. The insulating protective structure includes a plurality of first silicon carbonitride (SiCN) films and at least one first oxide thin film. Each first oxide thin film is between two adjacent ones of the plurality of first SiCN films.

Abstract: A semiconductor device may include first and second logic cells, which are on a substrate and are spaced apart from each other in a first direction, and each of which includes PMOSFET and NMOSFET regions, and first and second metal layers on the first and second logic cells, respectively. The first metal layer may include first, second, and third right interconnection lines, which extend in the first direction parallel to each other, with the second right interconnection line between the first and third right interconnection lines. The second metal layer may include a first left interconnection line. A shortest distance between the first right interconnection line and the first left interconnection line in the first direction may be defined as a first distance that is in a range from 12 nm to 18 nm.

Abstract: An integrated circuit device includes a lower metal wiring layer, an upper insulating film and an upper metal wiring layer on the lower metal wiring layer, and a conductive contact plug passing through the upper insulating film in a vertical direction to contact the lower and upper metal wiring layers, and the conductive contact plug has a tetragonal planar shape. Each of first contact sidewalls of the conductive contact plug in a first lateral direction extends from a corresponding one of upper line sidewalls of the upper metal wiring layer to the lower metal wiring layer in the vertical direction, and at least one of a pair of second contact sidewalls of the conductive contact plug in a second lateral direction extends in a direction inclined with respect to the vertical direction from a bottom surface of the upper metal wiring layer toward the lower metal wiring layer.

Abstract: Provided is an ion beam processing system including a plasma chamber including extraction opening for extracting an ion beam, an electron beam source unit disposed adjacent to the plasma chamber in a first direction and including an emission opening for emitting an electron beam, a substrate support unit provided to be movable in the first direction and to support a substrate, and a voltage supply unit configured to supply a voltage to the substrate support unit, wherein, when an electron beam emitted from the electron beam source unit is incident on the substrate, the voltage supply unit applies a positive voltage to the substrate support unit.

Abstract: A semiconductor device may include: a first source/drain pattern; a first active contact on the first source/drain pattern; a power line above the first active contact; and a first via contact connecting the first active contact to the power line, wherein the first via contact comprises a first side surface and a second side surface, which are opposite to each other in a first direction, the first side surface is inclined at a first angle to a top surface of the first active contact, the second side surface is inclined at a second angle to the top surface of the first active contact, and the first angle is an obtuse angle, and the second angle is an acute angle.

Abstract: A semiconductor device includes standard cells on a substrate, first interconnection lines extending in a first direction and connected to an active region and a gate structure, second interconnection lines extending in a second direction, the second interconnection lines including a first line and a second line electrically connected to the first interconnection lines, first vias electrically connecting at least one of the first interconnection lines and at least one of the second interconnection lines to each other, and a connection structure disposed on the second interconnection lines and connecting the first line and the second line to each other. The connection structure includes a first inclined via connected to the first line and inclined toward the second line, and a second inclined via connected to the second line and inclined toward the first line. Upper ends of the first and second inclined vias are connected to each other.

Abstract: A semiconductor device may include a device isolation layer on a substrate and defining active regions extending a first direction; gate structures intersecting the active regions and extending in a second direction; channel layers spaced apart from each other on the active regions and surrounded by the gate structures; and source/drain regions connected to the channel layers and in recessed regions of the active regions on both sides of the gate structures. First and second regions of the substrate respectively may be spaced apart by a first length and the second length from first ends of the gate structures in the second direction. The second length may be longer than the first length. An upper surface of the device isolation layer may have recessed portion on the first region of the substrate and a flat upper surface on the second region of the substrate.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: Disclosed is a method and system for providing a behavior data sales service. A behavior data sales service providing method, implemented by a computer system, may include collecting behavior data of each of activity entities; associating the behavior data with unique information of each of the activity entities; generating sales data of each of the activity entities by assigning a valid period for the unique information of each of the activity entities to the unique information of each of the activity entities; monitoring the valid period for the unique information of each of the activity entities in response to selling sales data of each of the activity entities to each of purchase entities; and repeatedly updating the unique information of each of the activity entities according to the valid period for the unique information of each of the activity entities.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch.. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Abstract: An ion beam apparatus may include a chamber assembly configured to hold a material and direct an ion beam on the material, a detector configured to detect a signal generated from the material based on the ion beam being directed on the material, and a controller configured to control at least one parameter associated with the chamber assembly based on the signal, such that at least one of an ion energy associated with the ion beam, an ion current associated with the ion beam, and an incident angle of the ion beam with respect to a top surface of the material is changed continuously with time.

Abstract: An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

Abstract: A method of forming fine patterns includes forming an upper mask layer on a substrate, forming preliminary mask patterns on the upper mask layer, and forming upper mask patterns by etching the upper mask layer using the preliminary mask patterns as etch masks. Forming the upper mask patterns includes etching the upper mask layer by performing an etching process using an ion beam. The upper mask patterns include a first upper mask pattern formed under each of the preliminary mask patterns, and a second upper mask pattern formed between the preliminary mask patterns in a plan view and spaced apart from the first upper mask pattern.