Abstract: A light emitting device including first, second, and third light emitting stacks each including first and second conductivity type semiconductor layers, a first lower contact electrode in ohmic contact with the first light emitting stack, and second and third lower contact electrodes respectively in ohmic contact with the second conductivity type semiconductor layers of the second and third light emitting stacks, in which the first lower contact electrode is disposed between the first and second light emitting stacks, the second and third lower contact electrodes are disposed between the second and third light emitting stacks, and the first, second, and third lower contact electrodes include transparent conductive oxide layers.

Abstract: A light emitting device including a first light emitting stack, a second light emitting stack, and a third light emitting stack each including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, a first adhesive layer bonding the first light emitting stack and the second light emitting stack, and a second adhesive layer bonding the second light emitting stack and the third light emitting stack, in which the second light emitting stack is disposed between the first light emitting stack and the third light emitting stack, and one of the first adhesive layer and the second adhesive layer electrically connects adjacent light emitting stacks.

Abstract: A method of manufacturing a semiconductor die stack structure includes: preparing a base die including a base die substrate and a base die inter-layer dielectric layer; forming a base die front-side bonding pad structure; preparing a bottom die having a bottom die substrate and bottom die through-electrode; forming a bottom die front-side bonding pad structure in the bottom die substrate; forming a base-bottom die stack structure where the bottom die front-side bonding pad structure is directly in contact with the base die front-side; forming a base die through-electrode vertically passing through the base die substrate and electrically connected to the base die front-side bonding pad structure; forming a base die back-side bump structure electrically connected to the base die through-electrode; stacking middle dies and a top die in the base-bottom die stack structure; and forming a bottom die back-side bump structure electrically connected to the bottom die through-electrode.

Abstract: In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.

Abstract: A semiconductor die stack structure includes a base die, a plurality of semiconductor die stack units, and bumps. Each of the plurality of semiconductor die stack units includes a lower semiconductor die and an upper semiconductor die. Each of the lower semiconductor die and the upper semiconductor die includes a body and a front-side pad structure. The front-side pad structure includes a front-side pad seed layer and a front-side pad pattern. The front-side pad pattern includes a first front-side pad portion, a second front-side pad portion, and a third front-side pad portion. The first front-side pad portion and the second front-side pad portion forms a staircase. The first front-side pad portion and the third front-side pad form a reverse staircase. The first front-side pad portion, the second front-side pad portion, and the third front-side pad include a same metal.

Abstract: A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.

Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.

Abstract: A ground electrode (100) positioned in the earth and a monitoring device (200) configured to measure a current and resistance of a ground line, where the monitoring device (200) includes a ground current sensing unit (210) configured to measure the current of the ground line, a resistance sensing unit (220) configured to measure ground resistance of the earth and an earth resistance rate, a voltage sensing unit (230) configured to check a voltage value of commercial power, a temperature and humidity sensing unit (240) configured to check a surrounding temperature and humidity of the monitoring device (200), and a monitoring unit (250) configured to confirm whether the ground current, ground resistance and earth resistance measured are abnormal values by compared with reference values classified based on the temperature and humidity measured.

Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.

Abstract: An apparatus for checking damage to a surge protector and automatically changing a surge protector includes a casing, a current inflow unit supplied with an external current, a current discharge unit configured to supply an inflow current to an external electronic device, surge protectors placed between the current inflow unit and the current discharge unit in parallel, selectively connected to the current inflow unit, and supplied with an electric current, a relay placed between the current inflow unit and the surge protectors and configured to selectively connect the surge protectors to the current inflow unit, and a surge protector damage check unit configured to check whether a surge protector connected to the current inflow unit has been damaged by applying a voltage between the current inflow unit and the current discharge unit.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.

Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Provided is a pharmaceutical composition for the treatment and prevention of alcoholic liver diseases, including cilostazol as an active ingredient. Cilostazol inhibits expression levels of TNF-? and FAS (fatty acid synthase) gene in a concentration-dependent manner, and also significantly inhibits the activity of caspase-3. Accordingly, cilostazol shows superior effects for the treatment or prevention of alcoholic liver diseases, in particular, alcoholic hepatitis compared to pentoxifylline which is conventionally used as a therapeutic agent for the treatment for alcoholic hepatitis. Thus, cilostazol is suitable for use as a drug for the treatment or prevention of alcoholic hepatitis.

Abstract: A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.