Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Abstract: A semiconductor die includes interlayer insulating layer, a signal horizontal metal interconnection and a power horizontal metal interconnection, a front-side passivation layer, a signal front-side bump structure and a power front-side bump structure, a signal vertical via plug, and a power vertical via plug over a front-side of a substrate; and a back-side insulating layer, a back-side metal plate layer, a back-side passivation layer, a signal back-side bump structure and a power back-side bump structure, a signal through-electrode, and a power through-electrode over a back-side of the substrate. Upper ends of the signal through-electrode and the power through-electrode protrude from the back-side surface of the substrate. The back-side metal plate layer is not to be electrically connected to the signal through-electrode. The back-side metal plate layer is electrically connected to the power bump structure.

Abstract: A method of manufacturing a semiconductor die stack structure includes: preparing a base die including a base die substrate and a base die inter-layer dielectric layer; forming a base die front-side bonding pad structure; preparing a bottom die having a bottom die substrate and bottom die through-electrode; forming a bottom die front-side bonding pad structure in the bottom die substrate; forming a base-bottom die stack structure where the bottom die front-side bonding pad structure is directly in contact with the base die front-side; forming a base die through-electrode vertically passing through the base die substrate and electrically connected to the base die front-side bonding pad structure; forming a base die back-side bump structure electrically connected to the base die through-electrode; stacking middle dies and a top die in the base-bottom die stack structure; and forming a bottom die back-side bump structure electrically connected to the bottom die through-electrode.

Abstract: In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.

Abstract: A semiconductor die stack structure includes a base die, a plurality of semiconductor die stack units, and bumps. Each of the plurality of semiconductor die stack units includes a lower semiconductor die and an upper semiconductor die. Each of the lower semiconductor die and the upper semiconductor die includes a body and a front-side pad structure. The front-side pad structure includes a front-side pad seed layer and a front-side pad pattern. The front-side pad pattern includes a first front-side pad portion, a second front-side pad portion, and a third front-side pad portion. The first front-side pad portion and the second front-side pad portion forms a staircase. The first front-side pad portion and the third front-side pad form a reverse staircase. The first front-side pad portion, the second front-side pad portion, and the third front-side pad include a same metal.

Abstract: A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.

Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Abstract: A radar detector enabling hands-free communication over a mobile phone by connecting the mobile phone to the radar detector. The radar detector includes a horn antenna; a signal-processing unit (SPU) for detecting a signal received by the horn antenna; a laser module for receiving a laser signal; a central processing unit (CPU) for controlling the SPU; a pulse delay unit for delaying or sustaining a CPU pulse; a sweep voltage generator unit for driving the SPU; a warning unit for warning the detected signal; an audio amplifier controller connected to the CPU and the warning unit to amplify an audio signal; and a connecting unit installed to connect the audio amplifier controller with a mobile phone. The connecting unit includes a microphone, a switch for reception of a signal from the mobile phone, and a connection portion for connection to the mobile phone.

Abstract: Disclosed is a fabrication method of UBM for flip chip interconnections of a semiconductor device, consisting of dipping a patterned wafer into a plating solution containing materials supplying nickel and copper ions, forming a copper layer at a predetermined current density for connection between a chip pad and a solder bump and for residual stress-buffering, and forming a nickel-copper alloy layer at an increased current density for prevention of diffusion between the solder and the pad. The method is advantageous in terms of low fabrication cost due to not requiring an etching process, while meeting the conditions of wettability, diffusion-barrier function and small residual stress required to form UBM on the patterned wafer.

Abstract: Disclosed is a fabrication method of UBM for flip chip interconnections of a semiconductor device, consisting of dipping a patterned wafer into a plating solution containing materials supplying nickel and copper ions, forming a copper layer at a predetermined current density for connection between a chip pad and a solder bump and for residual stress-buffering, and forming a nickel-copper alloy layer at an increased current density for prevention of diffusion between the solder and the pad. The method is advantageous in terms of low fabrication cost due to not requiring an etching process, while meeting the conditions of wettability, diffusion-barrier function and small residual stress required to form UBM on the patterned wafer.