Patents by Inventor Jong Yeon Lee
Jong Yeon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978759Abstract: A light emitting diode (LED) stack for a display including a substrate, a first LED stack disposed on the substrate, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, a first color filter interposed between the first LED stack and the second LED stack, and a second color filter interposed between the second LED stack and the third LED stack, in which the second LED stack and the third LED stack are configured to transmit light generated from the first LED stack to the outside, and the third LED stack is configured to transmit light generated from the second LED stack to the outside.Type: GrantFiled: July 2, 2021Date of Patent: May 7, 2024Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Chang Yeon Kim, Ho Joon Lee
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Patent number: 11975296Abstract: A pore-filled ion exchange polyelectrolyte composite membrane from which the surface ion exchange polyelectrolyte has been removed and a method of manufacturing the same are provided. The ion exchange polyelectrolyte composite membrane exhibits low film resistance and low in-plane-direction swelling degree, and has a smaller film-thickness than a commercial film, and thus, can be used for various purposes. In addition, since the pore-filled ion exchange polyelectrolyte composite membrane is continuously manufactured through a roll-to-roll process, the manufacturing process is simple, and manufacturing costs can be greatly reduced.Type: GrantFiled: April 29, 2019Date of Patent: May 7, 2024Assignee: Toray Advanced Materials Korea Inc.Inventors: Young Woo Choi, Mi Soon Lee, Tae Young Kim, Young Gi Yoon, Beom Jun Kim, Min Ho Seo, Chi Young Jung, Jong Min Lee, Nam-jo Jeong, Seung Cheol Yang, Ji Yeon Choi
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Patent number: 11969397Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.Type: GrantFiled: November 7, 2019Date of Patent: April 30, 2024Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Mi-La Cho, Dong-Yun Shin, Jong-Young Choi, Chul-Woo Yang, Sung-Hwan Park, Seon-Yeong Lee, Min-Jung Park, Joo-Yeon Jhun, Se-Young Kim, Hyeon-Beom Seo, Jae-Yoon Ryu, Keun-Hyung Cho
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Patent number: 11961750Abstract: A magnetic transfer apparatus includes: a magnetomotive force source providing magnetic flux, a first magnetic flux distribution circuit connected to one end of the magnetomotive force source, having a single input terminal and a plurality of output terminals, and distributing the magnetic flux, and a second magnetic flux distribution circuit connected to the other end of the magnetomotive force source, having a single output terminal and a plurality of input terminals, and collecting the distributed magnetic flux. The output terminals of the first magnetic flux distribution circuit are disposed to be adjacent to each other to form a pair with the input terminals of the second magnetic flux distribution circuit.Type: GrantFiled: November 29, 2021Date of Patent: April 16, 2024Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Tae-Yeon Seong, Da-Hoon Lee, Jong-Ho Kim
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Patent number: 11961742Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: August 23, 2021Date of Patent: April 16, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 11955262Abstract: An inductor includes a first magnetic body having a toroidal shape and having a ferrite; and a second magnetic body configured to be different from the first magnetic body and including a metal ribbon, wherein the second magnetic body includes an outer magnetic body disposed on an outer circumferential surface of the first magnetic body and an inner magnetic body disposed on an inner circumferential surface of the first magnetic body, and each of the outer magnetic body and inner magnetic body is wound in a plurality of layers in a circumferential direction of the first magnetic body.Type: GrantFiled: February 16, 2022Date of Patent: April 9, 2024Assignee: LG INNOTEK CO., LTD.Inventors: Mi Jin Lee, Ji Yeon Song, Yu Seon Kim, Jong Wook Lim, Seok Bae, Sang Won Lee
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Publication number: 20240105656Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.Type: ApplicationFiled: March 20, 2023Publication date: March 28, 2024Applicant: SK hynix Inc.Inventors: Jae Jun LEE, Jong Yeon KIM, Jong Hoon KIM, Ju Heon YANG, Mi Seon LEE
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Patent number: 11935912Abstract: A display apparatus including a thin film transistor (TFT) substrate; a first LED sub-unit, a second LED sub-unit, and a third LED sub-unit; first, second, third, and fourth electrode pads disposed between the TFT substrate and the first LED sub-unit; and connectors connecting the first, second, and third LED sub-units to a respective one of the electrode pads, in which the first, second, and third sub-units are configured to be independently driven; light generated from the first LED sub-unit is emitted to the outside of the display apparatus by passing through the second and third LED sub-units; light generated from the second LED sub-unit is emitted to the outside of the display apparatus by passing through the third LED sub-unit; and at least one of the connectors includes a first portion electrically connecting a first surface of the first LED sub-unit to the second electrode pad.Type: GrantFiled: June 22, 2022Date of Patent: March 19, 2024Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee, Chang Yeon Kim, Chung Hoon Lee
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Publication number: 20230378204Abstract: An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Seoksan KIM, Minwoong SEO, Myunglae CHU, Jong-yeon LEE, Min-Jun CHOI
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Patent number: 11756968Abstract: An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.Type: GrantFiled: May 25, 2020Date of Patent: September 12, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seoksan Kim, Minwoong Seo, Myunglae Chu, Jong-Yeon Lee, Min-Jun Choi
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Publication number: 20210091129Abstract: An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.Type: ApplicationFiled: May 25, 2020Publication date: March 25, 2021Inventors: SEOKSAN KIM, MINWOONG SEO, Myunglae CHU, Jong-yeon LEE, MIN-JUN CHOI
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Patent number: 6556422Abstract: A dielectric ceramic composition, a multi-layer ceramic capacitor and a manufacturing method characterized by superior dielectric properties. The ceramic capacitor includes a chip having a plurality of dielectric layers, a plurality of internal electrodes stacked alternately with the dielectric layers, and a pair of outer electrodes formed on both sides of the chip, with the composition of the dielectric layers including: 100 moles of barium calcium titanate BaCaxTiO3 (0.001≦x≦0.02), 0.5-4 moles of MgO, 0.01-0.5 moles of MnO, 0.1—2 moles of BaO, 0.1-2 moles of CaO, 1-4 moles of SiO2, and 0.1-3 moles of at least one or more compounds selected from the group consisting of Y2O3, Dy2O3, Ho203 and Er2O3. The capacitor thus manufactured satisfies the X7R standard and has superior dielectric properties, and the deviations of the dielectric properties are extremely low, thereby ensuring a high reliability.Type: GrantFiled: May 18, 2001Date of Patent: April 29, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Gyun Kim, Seong Won Cho, Seong Un Ma, Kang Heon Her, Jong Yeon Lee
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Publication number: 20020074154Abstract: A dielectric ceramic composition, a multi-layer ceramic capacitor using it and a manufacturing method therefor are disclosed, in which the dielectric properties are superior. The ceramic capacitor includes a chip having a plurality of dielectric layers 2, a plurality of internal electrodes 3 stacked alternately with the dielectric layers, and a pair of outer electrodes 4 formed on both sides of the chip, the composition of dielectric layers comprising: 100 moles of barium calcium titanate BaCaxTiO3(0.001≦x≦0.02), 0.5-4 moles of MgO, 0.01-0.5 moles of MnO, 0.1-2 moles of BaO, 0.1-2 moles of CaO, 1-4 moles of SiO2, and 0.1-3 moles of at least one or more compounds selected from the group consisting of Y2O3, Dy2O3, Ho2O3 and Er2O3. The capacitor thus manufactured satisfies the X7R standard has superior dielectric properties, and the deviations of the dielectric properties are extremely low, thereby ensuring a high reliability.Type: ApplicationFiled: May 18, 2001Publication date: June 20, 2002Applicant: Samsung Electro-Machanics Co., Ltd.Inventors: Han Gyun Kim, Seong Won Cho, Seong Un Ma, Kang Heon Her, Jong Yeon Lee