Abstract: A radio receiver device comprises an analogue-to-digital converter clocked by a first clock signal which receives a radio signal. A digital circuit portion receives a digital signal produced by the analogue-to-digital converter and comprises digital processing units clocked by a second clock derived from the first clock and which produce an output signal at an output sample rate. A counter clocked by the second clock counts samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag synchronised to the first clock. The counter is enabled when the flag is set and sets a trigger flag when the count exceeds a predetermined threshold. A buffer receives the output signal and is enabled when the trigger flag is set.

Abstract: According to an aspect, there is provided a finite state machine repair circuitry comprising: at least one control unit, and at least one memory for storing instructions to be executed by the at least one control unit, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry at least to perform: causing overriding at least one of one or more input and/or output signals of a finite state machine circuit by corresponding one or more override signals generated by the finite state machine repair circuitry so as to a form a channel mimicking operation of said finite state machine circuit.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: An integrated-circuit device comprising first and second radio systems. The first radio system comprises a first processor coupled to a first program memory and a first radio. The second radio system comprises a second processor coupled to a second program memory and a second radio. The device further comprises inter-processor communication (IPC) circuitry coupled to the first and second processors, for providing an IPC channel between the first and second processors. First software, stored in the first program memory for execution by the first processor comprises instructions for causing the first processor, in response to receiving a signal from the first radio, to send an electrical signal over the IPC channel to the second processor for causing second software stored in the second program memory to cause the second processor to send a command to the second radio.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A radio receiver device, arranged to receive a radio signal modulated with a plurality of data symbols, comprises an analogue-to-digital converter that is clocked by a first clock signal and is arranged to receive the radio signal and produce a digital signal. A digital circuit portion, arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units that are clocked by a second clock derived from the first clock and arranged to process the digital signal and produce an output signal at an output sample rate. A counter, clocked by the second clock, counts a number of samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag which is synchronised to the first clock. The counter is enabled only when the synchronised flag is set. The counter is arranged to set a trigger flag when the number of samples exceeds a predetermined threshold.

Abstract: A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.

Abstract: A method in a wireless communication device for diagnosing power supply failure in the wireless communication device is provided. The wireless communication device detects (301) an indication of power supply failure in the wireless communication device. When the indication of the power supply failure further indicates a non-active state of the wireless communication device or when the wireless communication device enters an error handling mode, the wireless communication device collects (302) diagnostic data from the PMU by means of a diagnostic engine (215) in the PMU. The wireless communication device then stores (303) the collected diagnostic data to a memory in the PMU. The data is related to the event resulting in the non-active state and/or to the latest event in a system of the wireless communication device or when the wireless communication device enters an error handling mode.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected, or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.

Abstract: A method of optimizing the number of output stages of a switched mode power supply features a dynamically-updated lookup table (LUT) storing historic output stage configuration data per system operating performance point (OPP). Upon entering an OPP, a margin is added to the historic optimal configuration. During operation at the OPP, the current drawn by the load is periodically monitored, and the number of output stages is dynamically adjusted, as needed (with low pass filtering to ensure stability). When the system exits the OPP, a running average of the optimal number of output stages for the OPP is updated with the actual number of output stages enabled in this iteration of the OPP. A running average of the deviation, or change in number of output stages enabled, is also maintained. The updated values are written to the LUT, for use in setting the initial output stage configuration the next time the same OPP is invoked.

Abstract: A method in a wireless communication device for diagnosing power supply failure in the wireless communication device is provided. The wireless communication device detects (301) an indication of power supply failure in the wireless communication device. When the indication of the power supply failure further indicates a non-active state of the wireless communication device or when the wireless communication device enters an error handling mode, the wireless communication device collects (302) diagnostic data from the PMU by means of a diagnostic engine (215) in the PMU. The wireless communication device then stores (303) the collected diagnostic data to a memory in the PMU. The data is related to the event resulting in the non-active state and/or to the latest event in a system of the wireless communication device or when the wireless communication device enters an error handling mode.

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Abstract: A method of optimizing the number of output stages of a switched mode power supply features a dynamically-updated lookup table (LUT) storing historic output stage configuration data per system operating performance point (OPP). Upon entering an OPP, a margin is added to the historic optimal configuration. During operation at the OPP, the current drawn by the load is periodically monitored, and the number of output stages is dynamically adjusted, as needed (with low pass filtering to ensure stability). When the system exits the OPP, a running average of the optimal number of output stages for the OPP is updated with the actual number of output stages enabled in this iteration of the OPP. A running average of the deviation, or change in number of output stages enabled, is also maintained. The updated values are written to the LUT, for use in setting the initial output stage configuration the next time the same OPP is invoked.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected, or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A method of compensating a direct-current offset coupled into a receiving path of a receiver, the receiving path having at least one gain factor adjustable by a gain control, which method first determines an amount of a direct-current offset present at a selected end point in the receiving path. A compensation quantity is set accordingly. In case of a forthcoming adjustment of the at least one gain factor by the gain control, the compensation quantity is then scaled with a scaling factor to prevent a direct-current step at the selected end point due to this forthcoming adjustment. The final compensation quantity is fed at a selected summing node into the receiving path. The invention is also directed to a corresponding receiver, an electronic device comprising such a receiver, a hardware component for such a receiver and to a corresponding software program product.

Abstract: Techniques for sample rate conversion are disclosed. In one exemplary embodiment, a sample rate conversion occurs between first samples having a sample rate defined by a first clock signal and second samples having a sample rate defined by a second clock signal. Using a conversion ratio and at a first rate defined by the first clock signal, a given second sample is determined from at least one first sample. A write pointer is updated for a buffer when second samples are written into the buffer. A read pointer is updated for the buffer when second samples are read from the buffer. The second samples are read from the buffer at a second rate defined by the second clock signal. The conversion ratio is modified based on the write and read pointers.