Patents by Inventor Jonnala gadda Nagendra Kumar

Jonnala gadda Nagendra Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12380625
    Abstract: The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: August 5, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Andrew Evan Gruber, Thomas Edwin Frisinger, Richard Hammerstone, Bo Du, Yongjun Xu
  • Patent number: 12353603
    Abstract: Systems, methods, and computer-readable media are provided for signing and executing graphics processing unit (GPU) commands. In some examples, a method can include receiving, by a GPU, one or more commands including one or more verification signatures generated using a processor, each verification signature of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each verification signature of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Avinash Seetharamaiah, Murat Balci, Jonnala Gadda Nagendra Kumar, Nigel Poole, Abhiraj Deshpande
  • Publication number: 20250173946
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a plurality of render targets (RTs) associated with a rendering process, where each of the plurality of RTs is associated with a subset of a graphics surface for the rendering process. The apparatus may also select at least one RT in the plurality of RTs based on the subset of the graphics surface associated with the at least one RT. Further, the apparatus may store the selected at least one RT in a buffer or a cache, or refraining from storing the selected at least one RT in the buffer or the cache.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Inventors: Md Wahidul ISLAM, Jonnala Gadda NAGENDRA KUMAR, Andrew Evan GRUBER, Avinash SEETHARAMAIAH, Tao WANG, Brendon Lewis JOHNSON, Thomas Edwin FRISINGER, Zhenbiao MA, Raghavendra NAGARAJ
  • Patent number: 12229864
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 18, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Eric Demers, Andrew Evan Gruber, Chun Yu, Baoguang Yang, Chihong Zhang, Yuehai Du, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, Gang Zhong, Zilin Ying, Fei Wei
  • Publication number: 20250022204
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for adaptive BVH rebuilds with biased cost functions for dynamic geometry. A graphics processor may obtain an indication of first BVH structure(s) including first nodes, where the first BVH structure(s) are representative of first geometry data for first primitives in first frame(s), where each of the first nodes is associated with first primitive(s), may detect a number of rays that intersect each of the first BVH structure(s) from direction(s) associated with the first frame(s), may update a cost function based on the number of rays and each of the direction(s), and may configure, based on the updated cost function, second BVH structure(s) including second nodes, where the second BVH structure(s) are representative of second geometry data for second primitives in second frame(s), where each of the second nodes is associated with second primitive(s).
    Type: Application
    Filed: July 12, 2023
    Publication date: January 16, 2025
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Alfredo Olegario SAUCEDO, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
  • Publication number: 20240296153
    Abstract: Aspects of the disclosure are directed to metadata updating. In accordance with one aspect, an apparatus includes an external memory unit configured for storing an original descriptor tag; a descriptor loading block coupled to the external memory, the descriptor loading block configured to fetch the original descriptor tag from the external memory for storage in an internal cache memory and further configured to compare the original descriptor tag stored in the internal cache memory to each of a plurality of original base values; and a remap table database coupled to the descriptor loading block, the remap table database configured to store the plurality of original base values, a plurality of updated base values and a plurality of updated miscellaneous base values.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 5, 2024
    Inventors: Liang LI, Andrew Evan GRUBER, Jonnala Gadda NAGENDRA KUMAR, Thomas Edwin FRISINGER, Zilin YING, Srihari Babu ALLA
  • Patent number: 12067666
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Eric Demers, Andrew Evan Gruber, Chun Yu, Chihong Zhang, Baoguang Yang, Yuehai Du, Gang Zhong, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
  • Patent number: 12056804
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: August 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Andrew Evan Gruber, Gang Zhong, Yun Du, Jonnala Gadda Nagendra Kumar
  • Patent number: 11978151
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 7, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
  • Publication number: 20240070964
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
  • Publication number: 20240046543
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Inventors: Yun DU, Eric DEMERS, Andrew Evan GRUBER, Chun YU, Baoguang YANG, Chihong ZHANG, Yuehai DU, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, Gang ZHONG, Zilin YING, Fei WEI
  • Patent number: 11893677
    Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, David Kirk McAllister
  • Publication number: 20240037840
    Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, David Kirk MCALLISTER
  • Publication number: 20230377240
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: Yun DU, Eric DEMERS, Andrew Evan GRUBER, Chun YU, Chihong ZHANG, Baoguang YANG, Yuehai DU, Gang ZHONG, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
  • Publication number: 20230343016
    Abstract: The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.
    Type: Application
    Filed: November 18, 2020
    Publication date: October 26, 2023
    Inventors: Srihari Babu ALLA, Jonnala Gadda NAGENDRA KUMAR, Avinash SEETHARAMAIAH, Andrew Evan GRUBER, Thomas Edwin FRISINGER, Richard HAMMERSTONE, Bo DU, Yongjun XU
  • Publication number: 20230290034
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Thomas Edwin FRISINGER, Richard HAMMERSTONE, Andrew Evan GRUBER, Gang ZHONG, Yun DU, Jonnala Gadda NAGENDRA KUMAR
  • Patent number: 11727631
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a color analysis on at least one first frame of a plurality of frames, the color analysis being performed based on at least one image in the at least one first frame. The apparatus may also generate a frequency map for at least one second frame of the plurality of frames based on the performed color analysis. Further, the apparatus may render the at least one second frame based on the frequency map for the at least one second frame, the at least one second frame being rendered after the at least one first frame.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 15, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Matthew Netsch, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
  • Patent number: 11694384
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 4, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Andrew Evan Gruber, Gang Zhong, Yun Du, Jonnala Gadda Nagendra Kumar
  • Patent number: 11682109
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 20, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kalyan Kumar Bhiravabhatla, Krishnaiah Gummidipudi, Ankit Kumar Singh, Andrew Evan Gruber, Pavan Kumar Akkaraju, Srihari Babu Alla, Jonnala Gadda Nagendra Kumar, Vishwanath Shashikant Nikam
  • Publication number: 20230086288
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a color analysis on at least one first frame of a plurality of frames, the color analysis being performed based on at least one image in the at least one first frame. The apparatus may also generate a frequency map for at least one second frame of the plurality of frames based on the performed color analysis. Further, the apparatus may render the at least one second frame based on the frequency map for the at least one second frame, the at least one second frame being rendered after the at least one first frame.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Matthew NETSCH, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR