Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract: A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell connected to a bit line, a test driver configured to share a node with the normal driver, and provide an additional current for a test to the write current through the shared node in response to a test mode control signal, and a mode control unit configured to control an operation according to the test mode by providing the test mode control signal to the test driver.

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract: A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell connected to a bit line, a test driver configured to share a node with the normal driver, and provide an additional current for a test to the write current through the shared node in response to a test mode control signal, and a mode control unit configured to control an operation according to the test mode by providing the test mode control signal to the test driver.

Abstract: A DC-DC voltage converter includes a current comparator converting a fixed reference voltage and an input voltage to a corresponding reference current and input current. The current comparator compares levels of the reference current and input current to output a control signal. A charge pump converts an output voltage to corresponding to a target voltage by performing a charge pumping operation in response to the control signal. An input voltage providing unit divides the output voltage to output the input voltage which is fed back into the current comparator, and as such is capable of reducing the area occupied by the DC-DC voltage converter in the semiconductor device and improving current consumption.

Abstract: A semiconductor memory device includes: a phase comparison unit for comparing a phase of a clock signal with a phase of a reference clock signal; a delay line for delaying the clock signal in response to the comparison result of the phase comparison unit to output the delayed clock signal as the reference clock signal; a first delay locking control unit for adjusting a delay amount of the delay line to generate a locking signal when a phase of an output signal output from the delay line is within a predetermined range; and a second delay locking control unit for adjusting a phase difference between the clock signal and the reference clock signal within a predetermined range in response to an activation of the locking signal so that the phase difference is corrected.

Abstract: A semiconductor memory device includes: a phase comparison unit for comparing a phase of a clock signal with a phase of a reference clock signal; a delay line for delaying the clock signal in response to the comparison result of the phase comparison unit to output the delayed clock signal as the reference clock signal; a first delay locking control unit for adjusting a delay amount of the delay line to generate a locking signal when a phase of an output signal output from the delay line is within a predetermined range; and a second delay locking control unit for adjusting a phase difference between the clock signal and the reference clock signal within a predetermined range in response to an activation of the locking signal so that the phase difference is corrected.